Abstract: A multi-port memory system includes a shared memory bank, multiple command decoders configured to receive refresh commands from multiple processors, and a refresh controller coupled to the shared memory bank and the command decoders, and configured to selectively apply refresh commands from the command decoders to the shared memory bank.

Abstract: A system having a memory device accessible by a plurality of processors is provided. The system includes a memory device, a first processor, and a second processor. The memory device has a first memory array part and a second memory array part. The first processor predominantly accesses the first memory array part of the memory device and selectively accesses the second memory array part of the memory device. The second processor predominantly accesses the second memory array part of the memory device and selectively accesses the first memory array part of the memory device.

Abstract: A semiconductor device includes a memory cell array, including at least one of a plurality of memory cells storing program data received from a flash memory, a row address buffer, which receives a row address signal in response to a first strobe signal, and a column address buffer, which receives a column address signal in response to a second strobe signal. The device further includes a write protection circuit, enabled/disabled in response to a first control signal, the write protection circuit outputting a masking control signal in response to the row address signal, the second strobe signal, and second control signals when enabled, and a column decoder, which decodes the column address signal in response to the masking control signal and enables at least one of a plurality of column selection lines of the memory cell array, corresponding to the decoded column address signal, or disables the column selection lines.

Abstract: An electrostatic discharge circuit between a first pad and a second pad including an electrostatic discharge circuit element, including a bipolar transistor path and a resistor path, the electrostatic discharge circuit element alternately discharging an electrostatic current through the bipolar transistor path and the resistor path.

Abstract: A memory system includes a first external device, a second external device, and a multi-port memory device connected to the first and second external devices. The multi-port memory system includes: a first port and a second port connected to the first and second external devices, respectively, a first bank group having at least one memory bank, the first bank group configured to be accessed by the first external device through the first data port; a second bank group having at least one memory bank, the second bank group configured to be accessed by the second external device through the second data port; a third bank group having at least one memory bank, wherein the third bank group is configured to be selectively accessed by the first external device through the first data port or the second external device through the second data port. The multi-port memory system may prevent data collisions which occur when two ports simultaneously attempt to access the same memory bank.

Abstract: A semiconductor device is provided. The semiconductor device includes a storage part storing an address for weak cells in a nonvolatile state; and a dynamic semiconductor memory device including: a memory cell array having normal cells and the weak cells to be refreshed; and a refresh control part performing a refresh operation for the weak cells, wherein a refresh period for the weak cells is shorter than a refresh period for the normal cells when the address applied in a refresh operation mode coincides with the address stored in the storage part.

Abstract: The present invention disclosed herein is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device incorporating a reverse diode. This device includes a plurality of source regions isolated from a drain region. A source region in close proximity to the drain region is a first diffusion structure in which a heavily doped diffusion layer of a second conductivity type is formed in a body region of a second conductivity type. Another source region is a second diffusion structure in which a heavily doped diffusion layer of a first conductivity type and a heavily doped diffusion layer of the second conductivity type are formed in the body region of the second conductivity type. An impurity diffusion structure of the source region in close proximity to the drain region is changed to be operated as a diode, thereby forming a strong current path to ESD (Electro-Static Discharge) or EOS (Electrical Over Stress). As a result, it is possible to prevent the device from being broken down.

Abstract: Provided are a reference voltage generating circuit and an internal voltage generating circuit for controlling an internal voltage level, where the reference voltage generating circuit includes a distributing unit, a clamping control unit, and a control unit; the distributing unit has a voltage level lower than that of an external power supply voltage in response to the external power supply voltage, and outputs via an output terminal a reference voltage which varies according to an operating mode; the clamping control unit is connected between the output terminal and a ground voltage, and clamps the voltage level of the reference voltage at a constant level in response to a control voltage having a voltage level which is lower than that of the reference voltage; the control unit increases or decreases the voltage level of the reference voltage in response to first and second operating mode signals; the control unit includes a first control transistor and a second control transistor; and the reference voltage

Abstract: A dental implant includes a fixture and an abutment in a body, and a head for a compaction drill is configured for implanting such an implant. The implant includes an upper abutment portion on which a denture is fixed, a fixture portion implanted in the jawbone and forming single or double threads, and a settling portion formed between the abutment portion and the fixture portion. The invention improves the stability of the implant, improves stabilization of the bone tissue affixed to the implant, effectively seals the socket from its surroundings and facilitates bonding between implant and jawbone. This is achieved because of the early healing of tissue around the implant and the greater surface area in contact with surrounding tissue. As a result, an artificial crown may be coupled with the implant during the same surgery.

Abstract: A semiconductor device includes a memory cell array, including at least one of a plurality of memory cells storing program data received from a flash memory, a row address buffer, which receives a row address signal in response to a first strobe signal, and a column address buffer, which receives a column address signal in response to a second strobe signal. The device further includes a write protection circuit, enabled/disabled in response to a first control signal, the write protection circuit outputting a masking control signal in response to the row address signal, the second strobe signal, and second control signals when enabled, and a column decoder, which decodes the column address signal in response to the masking control signal and enables at least one of a plurality of column selection lines of the memory cell array, corresponding to the decoded column address signal, or disables the column selection lines.

Abstract: A display data control circuit can include a sequentially accessed memory circuit that is configured to sequentially store/retrieve image data for display received via data pins of the sequentially accessed memory circuit and a timing controller circuit that is configured to provide addressing information to the sequentially accessed memory circuit via the data pins thereof.

Abstract: A multi-port volatile memory device includes a first port configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core is configured to store data received thereat and read requested stored data therefrom. A main interface circuit is coupled to the first port and configured to provide data to/from the volatile main memory core and the first port in a master mode and configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port is configured for data transfer to/from an external non-volatile memory device and the device. A sub interface circuit is coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.

Abstract: A dental implant includes a fixture and an abutment in a body, and a head for a compaction drill is configured for implanting such an implant. The implant includes an upper abutment portion on which a denture is fixed, a fixture portion implanted in the jawbone and forming single or double threads, and a settling portion formed between the abutment portion and the fixture portion. The invention improves the stability of the implant, improves stabilization of the bone tissue affixed to the implant, effectively seals the socket from its surroundings and facilitates bonding between implant and jawbone. This is achieved because of the early healing of tissue around the implant and the greater surface area in contact with surrounding tissue. As a result, an artificial crown may be coupled with the implant during the same surgery.

Abstract: Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer “on the fly” to enable variable data I/O widths during memory access operations.

Abstract: There is provided an integrated circuit device having an input/output electrostatic discharge (I/O ESD) protection cell. The integrated circuit device includes an I/O ESD protection cell comprising a VDD ESD protection element connected between an I/O pad and a VDD line, a ground voltage (VSS) ESD protection element connected between the I/O pad and a VSS line, and a power clamp element connected between the VDD line and the VSS line, and wherein the VDD ESD protection element, the power clamp element, and the VSS ESD protection element in the I/O ESD protection cell are adjacent to each other so they can be connected in a straight line or are arranged to partially overlap.

Abstract: A dental implant, which includes a fixture and an abutment in a body, and the head for a compaction drill for implanting an implant are provided. The implant comprises an upper abutment portion on which a denture is fixed, a fixture portion implanted in the jawbone and forming single or double threads and a settling portion formed between the abutment portion and the fixture portion. The invention improves the stability of the implant exceedingly, improves stabilization of the bone tissue affixed to the implant, effectively seals the socket from its surroundings, and facilitates bonding between implant and jawbone. This is achieved because of the early healing of tissue around the implant and the greater surface area in contact with surrounding tissue. As a result, an artificial crown may be coupled with the implant during the same surgery.

Abstract: Provided are a reference voltage generating circuit and an internal voltage generating circuit for controlling an internal voltage level, where the reference voltage generating circuit includes a distributing unit, a clamping control unit, and a control unit; the distributing unit has a voltage level lower than that of an external power supply voltage in response to the external power supply voltage, and outputs via an output terminal a reference voltage which varies according to an operating mode; the clamping control unit is connected between the output terminal and a ground voltage, and clamps the voltage level of the reference voltage at a constant level in response to a control voltage having a voltage level which is lower than that of the reference voltage; the control unit increases or decreases the voltage level of the reference voltage in response to first and second operating mode signals; the control unit includes a first control transistor and a second control transistor; and the reference voltage