Abstract: A system is configured to receive a word that includes a group of samples; randomly select a subset of the samples; identify first samples, from the subset, with a lowest level of reliability; select another subset of the samples; identify second samples, from the other subset, with a lowest level of reliability; and create a merged subset based on selected first samples and selected second samples. The system is also configured to select a further subset of the samples; identify third samples, from the further subset, with a lowest level of reliability; identify fourth samples, from the merged subset, associated with a lowest level of reliability; create another merged subset based on a greater probability that fourth samples than third samples are included in the other merged subset; and generate another word based a sample from the other merged subset; and process the word using the other word.

Abstract: A system receives a first word on which to perform error correction; identifies combinations in which encoded bits, within the first word, can be inverted; generates candidate words based on the first word and the combinations; decodes the candidate words; determines distances between the decoded words and the first word; selects, as a second word, one of the decoded words associated with a shortest distance; compares the second word to the first word to identify errors within the first word; generates a value to cause a reliability level of the first word to increase when a quantity of the errors is less than a threshold; generates another value to cause a reliability level of the first word to decrease when the quantity of the errors is not less than the threshold; and outputs a third word based on the first word, and the value or the other value.

Abstract: A system, method, and apparatus is disclosed for interpolation of an output of an analog to digital converter (ADC) to enable operation of the ADC at a sampling rate that is independent of the sampling rate for a DSP core so as to efficiently enable operation at higher date rates. According to one of the embodiments, an interpolation circuit is coupled between the ADC and DSP core and receives a first plurality of samples of data at the first data rate from the ADC and supplies a plurality of samples of second data at a second data rate to the DSP core; the second data rate being less than the first data rate. According to one of the embodiments, the interpolation circuit includes a memory and a FIR filter circuit having filter tap coefficient values selected to provide attenuation at high frequencies to reduce aliasing noise.

Abstract: A system is configured to receive a block of symbols, associated with a phase-modulated signal that includes data symbols that correspond to a payload associated with the signal, and control symbols; process the control symbols to identify an amount of phase noise associated with the control symbols; reset a phase, associated with each of the data symbols, based on the amount of phase noise and a reference phase; interleave the respective data samples, of each of the data symbols with other data samples, where the interleaved respective data samples cause errors, associated with the respective data samples, to be spread out among the other data samples and reduces an error rate relative to a prior data rate that existed before the interleaving; and perform forward error correction on the interleaved respective data samples.

Abstract: In one implementation, a device may include a voltage regulator circuit, a data processing circuit, and an error correction circuit, where the error correction circuit may correct errors in data processed by the data processing circuit to obtain error-corrected data and output an error-corrected version of the processed data. Additionally, an error monitor circuit may output an error signal indicative of a level of the errors in the processed data. A control circuit may receive the error signal and control the voltage regulator circuit to adjust, based on the error signal, the supply voltage to the data processing circuit. In some implementations, the control circuit may also base its decision to control the voltage regulator circuit based on available timing margins in the data processing circuit.

Abstract: A system, method, and apparatus is disclosed for enabling a constant modulus algorithm (CMA) to be reliably used for blind equalization training of an equalizer. According to one embodiment, received signals in a binary phase shift keying (BPSK) format are converted to a quadrature phase shift keying (QPSK) format, to which CMA processing can be reliably applied for equalization. According to another aspect of this embodiment, the equalized QPSK signals are rotated to convert the signals to an equalized BPSK format for output.

Abstract: Consistent with the present disclosure, data, in digital form, is received by a transmit node of an optical communication system, and converted to an analog signal by a digital-to-analog converter (DAC) to drive a modulator. The modulator, in turn, modulates light at one of a plurality of wavelengths in accordance with the received data forming a plurality of corresponding carriers. The carriers are modulated according to one of a plurality of modulation formats and then optically combined to form a superchannel of a constant maximum capacity, for example. Accordingly, the number of carriers and the bit rate for each carrier remain constant for each modulation format to realize a constant maximum capacity. The superchannel is then transmitted over an optical communication path to a receive node. At the receive node, the superchannel is optically demultiplexed from a plurality of other superchannels.

Abstract: Consistent with the present disclosure, a method and system for detecting a clock phase of an optical signal in a coherent receiver is provided that is insensitive to polarization mode dispersion (PMD) and other polarization effects in the optical communication system. The clock phase of the received signal is estimated by first calculating a phase shift between a pair of related frequency domain data outputs of a Fourier transform circuit. The calculated phase shift includes a phase component and a data spectrum component. The calculated phase shift is then averaged over a number of clock cycles to remove the data spectrum components thus enabling extraction of the phase component. A determinant function on the time averaged result is used to normalize any effects of PMD from the received signal and isolate the phase component. In this manner, the phase component is not dependent on the PMD effects in the optical communication system.

Abstract: Consistent with the present disclosure, a method and system for estimating chromatic dispersion of an optical signal in a coherent receiver is provided that is insensitive to polarization mode dispersion (PMD) and other polarization effects in the optical communication system. The effects of chromatic dispersion in the optical system are estimated by first calculating a phase shift between a pair of related frequency domain data outputs of a Fourier transform circuit. The calculated phase shift includes a linear phase component that is proportional to the chromatic dispersion, a DC constant phase component, and a data spectrum component. The calculated phase shift is then averaged over a number of clock cycles to remove the data spectrum components. The time averaged result is used to normalize any effects of PMD from the received signal. A slope of the linear phase component as a function of frequency is then calculated and used to estimate the value for chromatic dispersion.

Abstract: Consistent with an aspect of the present disclosure, an optical signal carrying data or information is supplied to photodetector circuitry that generates a corresponding analog signal. The analog signal may be amplified or otherwise processed and supplied to analog-to-digital conversion (ADC) circuitry, which samples the analog signal to provide a plurality of digital signals or samples. The timing of such sampling is in accordance with a clock signal supplied to the ADC circuitry. A phase detector is provided that detects and adjust the clock signal to have a desired phase based on frequency domain data that is output from a Fast Fourier transform (FFT) circuit that receives the digital samples. Preferably, the phase detector circuit is configured such that it need not receive all the frequency domain data output from the FFT at any given time in order to determine the clock phase.

Abstract: Consistent with the present disclosure, optical signals are modulated in accordance with a higher order QAM modulation format, such as 8-QAM, to carry customer data, for example. The optical signals are converted to corresponding electrical signals, which are then subject to further processing. In particular, phase data associated with the higher order QAM constellation is processed, such that the outer points of the constellation are rotated to have the same phase as the inner points. As a result, both the inner and outer points resemble a constellation, and both may be more readily processed using feedforward or feedback carrier recovery. After such carrier recovery, the phase data is further processed so that the outer points are rotated back and the customer data can be extracted from the phase data.

Abstract: A system, method, and apparatus is disclosed for interpolation of an output of an analog to digital converter (ADC) to enable operation of the ADC at a sampling rate that is independent of the sampling rate for a DSP core so as to efficiently enable operation at higher date rates. According to one of the embodiments, an interpolation circuit is coupled between the ADC and DSP core and receives a first plurality of samples of data at the first data rate from the ADC and supplies a plurality of samples of second data at a second data rate to the DSP core; the second data rate being less than the first data rate. According to one of the embodiments, the interpolation circuit includes a memory and a FIR filter circuit having filter tap coefficient values selected to provide attenuation at high frequencies to reduce aliasing noise.

Abstract: A system, method, and apparatus is disclosed for enabling a constant modulus algorithm (CMA) to be reliably used for blind equalization training of an equalizer. According to one embodiment, received signals in a binary phase shift keying (BPSK) format are converted to a quadrature phase shift keying (QPSK) format, to which CMA processing can be reliably applied for equalization. According to another aspect of this embodiment, the equalized QPSK signals are rotated to convert the signals to an equalized BPSK format for output.

Abstract: A method of synthesizing a modulated optical signal using a laser cascaded with an amplitude modulator. A phase drive signal VF(t) is derived for driving the laser to generate an optical carrier signal with a desired phase ?(t). An amplitude drive signal VS(t) is then derived for driving the amplitude modulator to impose a desired amplitude S(t) onto the optical carrier signal generated by the laser. The amplitude drive signal VS(t) is compensated for amplitude modulation of the optical carrier signal generated by the laser.