Patents by Inventor Han-Hsiang Huang
Han-Hsiang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021560Abstract: A semiconductor device includes a first connector, a second connector, and a redistribution structure disposed between the first connector and the second connector. The redistribution structure includes a first connection tree electrically connecting the first connector to the second connector. The first connection tree includes a plurality of first conductive pads disposed in a plurality of respective levels, and a plurality of first via structures each disposed between adjacent ones of the plurality of first conductive pads. Any lateral end of each of the plurality of first conductive pads is spaced from the first connector within a first minimum pitch associated with the second connector.Type: ApplicationFiled: July 14, 2022Publication date: January 18, 2024Applicant: Taiwan Semicondutor Manufacturing Company, Ltd.Inventors: Ting-Yu Yeh, Han-Hsiang Huang, Chun-Hsien Wen, Chih-Wei Chang
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Publication number: 20240014120Abstract: A package structure includes a circuit substrate, a semiconductor package, first bump structures and second bump structures. The semiconductor package is disposed on the circuit substrate, wherein the semiconductor package includes a center region and side regions surrounding the center region. The first bump structures are disposed on the center region of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate. The second bump structures are disposed on the side regions of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate, wherein the first bump structures and the second bump structures have different heights and different shapes.Type: ApplicationFiled: September 22, 2023Publication date: January 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Sheng Lin, Han-Hsiang Huang, Chien-Sheng Chen, Shu-Shen Yeh, Shin-Puu Jeng
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Publication number: 20230411345Abstract: A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.Type: ApplicationFiled: June 10, 2022Publication date: December 21, 2023Inventors: Han-Hsiang Huang, Yen-Hao Chen, Chien-Sheng Chen, Shin-Puu Jeng
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Patent number: 11835979Abstract: A device includes a first impedance; a reference current generation circuit configured to generate a reference current according to a first potential difference, a reference voltage, and a first impedance value of the first impedance; a current mirror circuit configured to output an output current having a first ratio to the reference current according to the reference current; a second impedance configured to generate an output voltage according to a second impedance value of the second impedance, a voltage of a first node which is the same as the first potential difference, and the output current; and a negative feedback circuit configured to generate a feedback voltage according to the voltage of the first node, and adjust the output voltage according to the feedback voltage. There is a second ratio that is inversely proportional to the first ratio between the second impedance value and the first impedance value.Type: GrantFiled: July 22, 2022Date of Patent: December 5, 2023Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Han-Hsiang Huang
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Patent number: 11823887Abstract: A package structure includes a circuit substrate, a semiconductor package, first bump structures and second bump structures. The semiconductor package is disposed on the circuit substrate, wherein the semiconductor package includes a center region and side regions surrounding the center region. The first bump structures are disposed on the center region of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate. The second bump structures are disposed on the side regions of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate, wherein the first bump structures and the second bump structures have different heights and different shapes.Type: GrantFiled: July 15, 2021Date of Patent: November 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Sheng Lin, Han-Hsiang Huang, Chien-Sheng Chen, Shu-Shen Yeh, Shin-Puu Jeng
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Publication number: 20230369287Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.Type: ApplicationFiled: July 18, 2023Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
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Publication number: 20230352428Abstract: A semiconductor structure includes a semiconductor die containing an array of first bonding structures. Each of the first bonding structures includes a first metal pad located within a dielectric material layer and a basin-shaped underbump metallization (UBM) pad located within a respective opening in a passivation dielectric layer and contacting the first metal pad. An interposer includes an array of second bonding structures, wherein each of the second bonding structures includes an underbump metallization (UBM) pillar having a respective cylindrical shape. The semiconductor die is bonded to the interposer through an array of solder material portions that are bonded to a respective one of the first-type bonding structures and to a respective one of the second-type bonding structures.Type: ApplicationFiled: April 28, 2022Publication date: November 2, 2023Inventors: Yen-Hao Chen, Han-Hsiang Huang, Yu-Sheng Lin, Chien-Sheng Chen, Shin-Puu Jeng
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Publication number: 20230317577Abstract: An interconnect structure includes a lower pad including a first conductive layer having a first diameter, and a second conductive layer on the first conductive layer and having a second diameter less than the first diameter, an upper bump on the lower pad and having a third diameter less than the first diameter, and a solder joint between the upper bump and the lower pad.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Wei-Chieh HSU, Han-Hsiang Huang, Yu-Sheng Lin, Chien-Sheng Chen, Shin-Puu Jeng
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Patent number: 11756928Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.Type: GrantFiled: April 22, 2022Date of Patent: September 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
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Publication number: 20230035977Abstract: A device includes a first impedance; a reference current generation circuit configured to generate a reference current according to a first potential difference, a reference voltage, and a first impedance value of the first impedance; a current mirror circuit configured to output an output current having a first ratio to the reference current according to the reference current; a second impedance configured to generate an output voltage according to a second impedance value of the second impedance, a voltage of a first node which is the same as the first potential difference, and the output current; and a negative feedback circuit configured to generate a feedback voltage according to the voltage of the first node, and adjust the output voltage according to the feedback voltage. There is a second ratio that is inversely proportional to the first ratio between the second impedance value and the first impedance value.Type: ApplicationFiled: July 22, 2022Publication date: February 2, 2023Applicant: REALTEK SEMICONDUCTOR CORP.Inventor: Han-Hsiang Huang
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Patent number: 11526189Abstract: A voltage reduction circuit for a bandgap reference voltage circuit is provided, and the voltage reduction circuit includes a first transistor, a current mirror circuit, a voltage dividing circuit, an output resistor, and a fourth transistor. The first transistor receives an initial bandgap reference voltage from the bandgap reference voltage circuit. The voltage dividing circuit has a voltage dividing node for outputting a first dividing voltage. The fourth transistor receives the first divided voltage. The current mirror circuit forms a first current on the voltage dividing circuit through the first transistor, and mirrors the first current to the output resistor to form a second current. The voltage dividing circuit and the output resistor each have a first temperature characteristic, the first transistor and the fourth transistor each have a second temperature characteristic, thereby generating, a reference voltage independent of temperature and lower than the initial bandgap reference voltage.Type: GrantFiled: May 31, 2021Date of Patent: December 13, 2022Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Han-Hsiang Huang
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Publication number: 20220302011Abstract: A package structure includes a circuit substrate, a semiconductor package, first bump structures and second bump structures. The semiconductor package is disposed on the circuit substrate, wherein the semiconductor package includes a center region and side regions surrounding the center region. The first bump structures are disposed on the center region of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate. The second bump structures are disposed on the side regions of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate, wherein the first bump structures and the second bump structures have different heights and different shapes.Type: ApplicationFiled: July 15, 2021Publication date: September 22, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Sheng Lin, Han-Hsiang Huang, Chien-Sheng Chen, Shu-Shen Yeh, Shin-Puu Jeng
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Publication number: 20220246579Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.Type: ApplicationFiled: April 22, 2022Publication date: August 4, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
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Patent number: 11342306Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.Type: GrantFiled: August 30, 2020Date of Patent: May 24, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
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Publication number: 20220011804Abstract: A voltage reduction circuit for a bandgap reference voltage circuit is provided, and the voltage reduction circuit includes a first transistor, a current mirror circuit, a voltage dividing circuit, an output resistor, and a fourth transistor. The first transistor receives an initial bandgap reference voltage from the bandgap reference voltage circuit. The voltage dividing circuit has a voltage dividing node for outputting a first dividing voltage. The fourth transistor receives the first divided voltage. The current mirror circuit forms a first current on the voltage dividing circuit through the first transistor, and mirrors the first current to the output resistor to form a second current. The voltage dividing circuit and the output resistor each have a first temperature characteristic, the first transistor and the fourth transistor each have a second temperature characteristic, thereby generating, a reference voltage independent of temperature and lower than the initial bandgap reference voltage.Type: ApplicationFiled: May 31, 2021Publication date: January 13, 2022Inventor: HAN-HSIANG HUANG
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Patent number: 11216021Abstract: A current generation circuit includes a temperature sensing circuit, a resistor element having a resistance, and a current mirror circuit. The temperature sensing circuit is configured to generate a reference voltage having corresponding magnitude according to a temperature of the current generation circuit. The resistor element is coupled with the temperature sensing circuit, and is configured to determine magnitude of a reference current according to the reference voltage and the resistance. The current mirror circuit is coupled with the temperature sensing circuit, and is configured to generate an output current according to the reference current. The temperature sensing circuit and the resistor element both have positive temperature coefficients or negative temperature coefficients.Type: GrantFiled: November 6, 2020Date of Patent: January 4, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventor: Han-Hsiang Huang
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Patent number: 11189596Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.Type: GrantFiled: July 14, 2020Date of Patent: November 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
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Publication number: 20210157352Abstract: A current generation circuit includes a temperature sensing circuit, a resistor element having a resistance, and a current mirror circuit. The temperature sensing circuit is configured to generate a reference voltage having corresponding magnitude according to a temperature of the current generation circuit. The resistor element is coupled with the temperature sensing circuit, and is configured to determine magnitude of a reference current according to the reference voltage and the resistance. The current mirror circuit is coupled with the temperature sensing circuit, and is configured to generate an output current according to the reference current. The temperature sensing circuit and the resistor element both have positive temperature coefficients or negative temperature coefficients.Type: ApplicationFiled: November 6, 2020Publication date: May 27, 2021Inventor: Han-Hsiang HUANG
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Publication number: 20200395335Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.Type: ApplicationFiled: August 30, 2020Publication date: December 17, 2020Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
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Publication number: 20200343220Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.Type: ApplicationFiled: July 14, 2020Publication date: October 29, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee