Patents by Inventor Han-Hsiang Huang

Han-Hsiang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10763239
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Publication number: 20190131273
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 2, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Patent number: 9263941
    Abstract: A resonant converter with power factor correction includes a power-obtaining circuit, an energy-storage element and an energy-transferred circuit. The power-obtaining circuit is used for receiving an input line voltage. The energy-storage element is coupled between the power-obtaining circuit and the energy-transferred circuit. The energy-transferred circuit is used for generating an output power. In a first time period, based on a first control signal, the energy-storage element and the power-obtaining circuit operate a soft switching so that the energy-storage element is charged to obtain the input line power and generate an energy-storage voltage. In a second time period, based on a second control signal, the energy-storage element and the energy-transferred circuit operate a soft switching so that the energy-storage element is discharged to make the energy-storage voltage converted into the output power.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: February 16, 2016
    Assignee: MACROBLOCK, INC.
    Inventors: Lon-Kou Chang, Yi-Wen Huang, Han-Hsiang Huang
  • Patent number: 8937463
    Abstract: A common-core power factor correction resonant converter includes an energy-transforming circuit. The energy-transforming circuit receives an input line voltage and generates an output power. The energy-transforming circuit includes a coupling inductor and a charge-storage capacitor. The coupling inductor and the charge-storage capacitor are charged by the input line voltage in response to a control signal, so as to generate a charge-storage capacitor voltage. When the charge-storage capacitor voltage is charged to a preset voltage level, the coupling inductor and the charge-storage capacitor are discharged according to the control signal. Then, the energy in the coupling inductor and the charge-storage capacitor is transformed to the output load and provide the output voltage or current regulation.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: January 20, 2015
    Assignee: Macroblock, Inc.
    Inventors: Lon-Kou Chang, Yi-Wen Huang, Han-Hsiang Huang
  • Patent number: 8787051
    Abstract: The disclosure provides a method for controlling an equivalent resistance of a converter. The method includes receiving a power source input signal, generating a first control signal according to a voltage level and a state of the power source input signal to adjust an equivalent resistance of the voltage conversion module and cause the voltage conversion module to operate in the damper mode or the converter mode, when the voltage conversion module operates in the converter mode converting the power source input signal to an output signal, and when the voltage conversion module operates in the damper mode detecting the voltage level or the current level of the power source input signal, and adjusting the equivalent resistance so that the voltage conversion module could operate in the bleeder mode or the converter mode to convert the power source input signal to the output signal.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 22, 2014
    Assignee: Macroblock, Inc.
    Inventors: Lon-Kou Chang, Yi-Wen Huang, Han-Hsiang Huang
  • Publication number: 20140002035
    Abstract: A common-core power factor correction resonant converter includes an energy-transforming circuit. The energy-transforming circuit receives an input line voltage and generates an output power. The energy-transforming circuit includes a coupling inductor and a charge-storage capacitor. The coupling inductor and the charge-storage capacitor are charged by the input line voltage in response to a control signal, so as to generate a charge-storage capacitor voltage. When the charge-storage capacitor voltage is charged to a preset voltage level, the coupling inductor and the charge-storage capacitor are discharged according to the control signal. Then, the energy in the coupling inductor and the charge-storage capacitor is transformed to the output load and provide the output voltage or current regulation.
    Type: Application
    Filed: December 14, 2012
    Publication date: January 2, 2014
    Applicant: MACROBLOCK, INC.
    Inventors: Lon-Kou Chang, Yi-Wen Huang, Han-Hsiang Huang
  • Patent number: 7557423
    Abstract: A semiconductor structure includes an inductor; and a semiconductor substrate underlying the inductor, having a discontinuous material density across a plane underneath and in parallel with the inductor, thereby reducing eddy currents induced by an electrical current flowing through the inductor.
    Type: Grant
    Filed: September 5, 2007
    Date of Patent: July 7, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Ming Ching, Chen Chen-Shien, Han-Hsiang Huang, Chih-Hua Chen, Chen-Cheng Kuo
  • Publication number: 20090057823
    Abstract: A semiconductor structure includes an inductor; and a semiconductor substrate underlying the inductor, having a discontinuous material density across a plane underneath and in parallel with the inductor, thereby reducing eddy currents induced by an electrical current flowing through the inductor.
    Type: Application
    Filed: September 5, 2007
    Publication date: March 5, 2009
    Inventors: Kai Ming Ching, Chen Chen-Shien, Han-Hsiang Huang, Chih-Hua Chen, Chen-Cheng Kuo
  • Patent number: 6229702
    Abstract: A ball grid array semiconductor package includes a substrate, a die mounted on the substrate and electrically connected to the substrate by bonding wires, a heat ring mounted on the substrate to surround the die and the bonding wires, and a heat slug mounted on the heat ring to entirely cover the die and the bonding wires thereby providing improved heat dissipation efficiency and overall electrical performance. Encapsulation material is filled into an inner space surrounded by the heat ring, heat slug and substrate to form an encapsulant for protecting the die and bonding wires. The heat ring and heat slug has at least a portion of surface area sequentially coated with a metal medium layer and an insulation layer to enhance the bonding degree between the encapsulant and the heat ring and heat slug.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: May 8, 2001
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Su Tao, Chin-Long Wu, Tai-Chun Huang, Han-Hsiang Huang, Shih-Kuang Chen, Shin-Hua Chao
  • Patent number: 6191360
    Abstract: A BGA package includes a substrate, a chip, and a heat spreader. The spreader covers the chip, a bottom part of the spreader is mounted on an upper surface of the substrate by an adhesive. The spreader shields Electro Magnetic Interference to the chip. In addition, the substrate is made of a built-up PCB.
    Type: Grant
    Filed: April 26, 1999
    Date of Patent: February 20, 2001
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Su Tao, Han-Hsiang Huang, Kun-Ching Chen, Chun-Chi Lee