Patents by Inventor Han Huang

Han Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230099381
    Abstract: A method includes: determining a mutation frequency for each residue in a wild-type spike protein of a specific virus; for each residue in the protein, counting a total number of contact residues related to said each residue and P antibodies based on P entries of protein structure data; for each residue in the protein, for a condition that said each residue mutates into one common amino acid residue, determining a normalized binding free energy value using a pre-established model based on the protein structure data, and determining a mutation effect score based on the mutation frequency, the total number of contact residues and the normalized binding free energy value; generating a mutation effect epitope map related to the mutation effect scores determined for all residues in the protein and all common amino acid residues; and determining, based on the map, a region in the protein as a target epitope.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 30, 2023
    Inventors: Yi-Ting CHEN, Sing-Han HUANG, Ching-Yung LIN, Xiang-Yu LIN, Cheng-Tang WANG
  • Publication number: 20230098704
    Abstract: A heater device with a memory unit includes a first transistor, a second transistor, a memory unit and a heater. The first terminal of the second transistor and the first terminal of the first transistor are electrically connected to each other. The memory unit is electrically connected to the second terminal of the first transistor. The heater is electrically connected to the second terminal of the second transistor.
    Type: Application
    Filed: August 19, 2022
    Publication date: March 30, 2023
    Inventors: Po-Han HUANG, Tao-Sheng CHANG, Te-Yu LEE
  • Patent number: 11616974
    Abstract: A method of coding video data, including constructing a history-based motion vector prediction (HMVP) candidate history table that includes motion vector information of previously coded blocks that extend beyond adjacent neighboring blocks of a current block, constructing a motion vector predictor list, and adding one or more HMVP candidates from the HMVP candidate history table to the motion vector predictor list. Adding the one or more HMVP candidates from the HMVP candidate history table comprises comparing a first HMVP candidate in the HMVP candidate history table to two entries in the motion vector predictor list and no other entries, and adding the first HMVP candidate to the motion vector predictor list when the first HMVP candidate is different than both of the two entries in the motion vector predictor list. The method also includes coding the current block of video data using the motion vector predictor list.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: March 28, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Yu Han, Wei-Jung Chien, Han Huang, Marta Karczewicz
  • Publication number: 20230089741
    Abstract: An example method of encoding or decoding video data includes determining a motion vector for a block of video data using a decoder side motion vector derivation process that includes performing an iterative search process, wherein performing the iterative search process includes: determining a minimum cost through a previous search iteration; updating an overall minimum cost through a current search iteration; and terminating the iterative search process early based on a comparison of the minimum cost through the previous search iteration and the overall minimum cost through the current search iteration; and encoding or decoding the block of video data using the motion vector.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 23, 2023
    Inventors: Vadim Seregin, Han Huang, Marta Karczewicz
  • Patent number: 11611759
    Abstract: An example device for coding video data determines for a first block of the video data whether to use a sub-block merge mode. Based on the determination not to use the sub-block merge mode for the first block, the device determines whether to use a merge mode with blending for the first block. Based on the determination to use the merge mode with blending for the first block, the device codes the first block with the merge mode with blending.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: March 21, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Han Huang, Wei-Jung Chien, Vadim Seregin, Marta Karczewicz
  • Publication number: 20230079743
    Abstract: A method of decoding video data may comprise determining merge candidates for a block of video data and determining if a merge candidate of the merge candidates includes an additional inter prediction signal. If a merge candidate includes an additional inter prediction signal, the method may include disabling at least one decoder side motion vector derivation technique for use on a base prediction signal of the block of video data.
    Type: Application
    Filed: August 31, 2022
    Publication date: March 16, 2023
    Inventors: Han Huang, Yan Zhang, Vadim Seregin, Marta Karczewicz
  • Publication number: 20230082326
    Abstract: There is provided a method for training a neural network system by reinforcement learning, the neural network system being configured to receive an input observation characterizing a state of an environment interacted with by an agent and to select and output an action in accordance with a policy that aims to satisfy a plurality of objectives. The method comprises obtaining a set of one or more trajectories. Each trajectory comprises a state of an environment, an action applied by the agent to the environment according to a previous policy in response to the state, and a set of rewards for the action, each reward relating to a corresponding objective of the plurality of objectives. The method further comprises determining an action-value function for each of the plurality of objectives based on the set of one or more trajectories.
    Type: Application
    Filed: February 8, 2021
    Publication date: March 16, 2023
    Inventors: Abbas Abdolmaleki, Sandy Han Huang
  • Patent number: 11603883
    Abstract: A roller type linear guideway includes: a rail, a sliding block sleeved on the rail, and end cover units installed at two ends of the sliding block. One of the end cover units includes a first cover plate, a second cover plate, an open end cover, and an outer end cover. The first cover plate includes a plurality of penetrating holes communicating with the non-load passages, the second cover plate is installed on the first cover plate and includes holes connected to the penetrating holes, and the open end cover is installed on one end of the sliding block and includes through holes communicating with the holes. The outer end cover closes the through holes to allow circulation of multiple rolling elements. The through holes, the holes, and the penetrating holes are connected to the non-load passages, so four rows of rolling elements can be filled simultaneously.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: March 14, 2023
    Assignee: Hiwin Technologies Corp.
    Inventors: Guan-Ting Lin, Chao-Syuan Cai, Wen-Hao Yang, Bo-Han Huang
  • Patent number: 11606575
    Abstract: An example device for coding video data includes a memory configured to store video data; and one or more processing units implemented in circuitry and configured to: store motion information for a first coding tree unit (CTU) line of a picture in a first history motion vector predictor (MVP) buffer of the memory; reset a second history MVP buffer of the memory; and after resetting the second history MVP buffer, store motion information for a second CTU line of the picture in the second history MVP buffer, the second CTU line being different than the first CTU line. Separate threads of a video coding process executed by the one or more processors may process respective CTU lines, in some examples.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 14, 2023
    Assignee: Qualcomm Incorporated
    Inventors: Luong Pham Van, Wei-Jung Chien, Vadim Seregin, Marta Karczewicz, Han Huang
  • Publication number: 20230067209
    Abstract: A testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. The circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. The testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. The first conductive line is connected to the main portion. The socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Ting Chen, Cheng-Han Huang, Kuang-Hua Wang
  • Publication number: 20230062148
    Abstract: A method for manufacturing a semiconductor device includes forming a photoresist layer comprising a photoresist composition over a substrate to form a photoresist-coated substrate. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern in the photoresist layer. The latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a patterned photoresist layer exposing a portion of the substrate, and a purge gas is applied to the patterned photoresist layer.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Wei-Han HUANG, Alston CHANG, Yao-Hwan KAO
  • Patent number: 11588470
    Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate, a first electronic component and a support component. The first electronic component is disposed on the substrate. The first electronic component has a backside surface facing a first surface of the substrate. The support component is disposed between the backside surface of the first electronic component and the first surface of the substrate. The backside surface of the first electronic component has a first portion connected to the support component and a second portion exposed from the support component.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 21, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Ching-Han Huang, Kuo-Hua Lai, Hui-Chung Liu
  • Publication number: 20230043227
    Abstract: A system comprising a plurality of nodes communicatively coupled to one another via at least one wireless link and a controller communicatively coupled to at least one of the nodes, wherein the controller (1) coordinates at least one scan that measures interference introduced into the wireless link, (2) identifies, based at least in part on the scan, one or more characteristics of the wireless link, (3) determines, based at least in part on the characteristics of the wireless link, that the node is eligible for a tapered codebook that, when implemented, modifies at least one feature of an antenna array that supports the wireless link in connection with the node, and then (4) directs the node to implement the tapered codebook. Various other apparatuses, systems, and methods are also disclosed.
    Type: Application
    Filed: September 29, 2022
    Publication date: February 9, 2023
    Inventors: Lisi Jiang, Ahmed Gamal Helmy Mohamed, Brian Dunn, Po Han Huang, Krishna Srikanth Gomadam
  • Publication number: 20230038785
    Abstract: A semiconductor apparatus and a method for collecting residues of curable material are provided. The semiconductor apparatus includes a chamber containing a wafer cassette, and a collecting module disposed in the chamber for collecting residues of curable material in the chamber. The collecting module includes a flow-directing structure disposed below a ceiling of the chamber, a baffle structure disposed below the flow-directing structure, and a tray disposed on the wafer cassette. The flow-directing structure includes a first hollow region, the baffle structure includes a second hollow region, and the tray is moved together with the wafer cassette to pass through the second hollow region of the baffle structure and is positioned to cover the first hollow region of the flow-directing structure.
    Type: Application
    Filed: August 5, 2021
    Publication date: February 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Cheng Lin, Pin-Yi Hsin, Ching Shun Lee, Bo-Han Huang, Cheng-Tsung Tu
  • Patent number: 11570434
    Abstract: A method of decoding video data includes determining that a geometric partition mode is enabled for a current block of the video data and determining a split line dividing the current block into a first partition and a second partition, where determining the split line comprises selecting an angle for the split line from a plurality of angles, Each angle of the plurality of angles corresponding to an N:M ratio of samples of the current block, where N and M are integers. The split line is not at a corner of the current block. The method further includes determining geometric mode weights for the current block using the angle of the split line, generating a first prediction block using motion information for the first partition, and generating a second prediction block using motion information for the second partition.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: January 31, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kevin Pascal Andre Reuze, Han Huang, Vadim Seregin, Marta Karczewicz
  • Patent number: 11565934
    Abstract: A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: January 31, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Hsuan Tsai, Lu-Ming Lai, Chien-Wei Fang, Ching-Han Huang
  • Patent number: 11570442
    Abstract: An example video coding device is configured to: code a first set of motion information for a current block of video data partitioned into a first partition and a second partition according to a non-rectangular partition mode, the first set of motion information referring to a reference picture list and being associated with the first partition; after coding the first set of motion information, code a second set of motion information for the current block referring to the reference picture list and that is associated with the second partition; in response to the first set of motion information and the second set of motion information both referring to the reference picture list, store the second set of motion information for the current block; and predict subsequent motion information of a subsequent block of the video data that neighbors the current block using the stored second set of motion information.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: January 31, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kevin Pascal Andre Reuze, Chun-Chi Chen, Wei-Jung Chien, Han Huang, Marta Karczewicz, Vadim Seregin
  • Publication number: 20230025347
    Abstract: Disclosed are embodiments of a graphics scene detection technique that provides an adaptive scale factor dependent on an image quality, such that certain images may be downscaled prior to being displayed to preserve system resources without significantly affecting image quality for a user. The inventors recognized and appreciated that certain images may be presented at a lower resolution to a user without being perceived as lower image quality. Some aspects provide a scene detection module that determines a quality score from a graphic command output for an image. Depending on the quality score, the scene detection module may output a quality-aware scale factor that can be applied to reduce pixel resolution of an image before displaying the image to a user. Resultingly, the computing device may be improved by saving system resources including memory bandwidth, processing power for other apps or instances, without negatively affecting visual perception of the scene.
    Type: Application
    Filed: June 24, 2022
    Publication date: January 26, 2023
    Applicant: MediaTek Inc.
    Inventors: Jen-Jung Cheng, Shih-Chin Lin, Du-Xiu Li, Ying-Chieh Chen, Kun-Han Huang
  • Publication number: 20230029084
    Abstract: Provided is Lactobacillus paracasei TCI727, deposited in the Deutsche Sammlung von Mikroorganismen und Zellkulturen GmbH (DSMZ) with a deposit number of DSM 33756. A method for improving calcium absorption of a subject in need thereof by using the Lactobacillus paracasei TCI727 or metabolites thereof is also provided. The method includes administering to the subject an effective amount of a composition comprising the Lactobacillus paracasei TCI727 or the metabolites thereof.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 26, 2023
    Inventors: YUNG-HSIANG LIN, CHU-HAN HUANG
  • Publication number: 20230005513
    Abstract: The present application discloses an interface transformer. The interface transformer includes a first clock generator, a combinational circuit, and a second clock generator. The first clock generator generates an intermediate clock signal according to an input clock signal. A rising edge of the input clock signal precedes a rising edge of the intermediate clock signal, and a falling edge of the intermediate clock signal precedes a falling edge of the input clock signal. The combinational circuit generates a mask clock signal by delaying the intermediate clock signal. The second clock generator generates a transformed clock signal according to the input clock signal and the mask clock signal. The transformed clock signal has two pulses within a cycle of the input clock signal.
    Type: Application
    Filed: October 14, 2021
    Publication date: January 5, 2023
    Inventors: I-HAN HUANG, CHIH-CHIEH CHIU