Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A device for generating restoration data by descrambling scramble data includes a linear feedback shift register configured to receive a first clock including a plurality of edges and sequentially generate a plurality of seeds including first to N?1th seeds (where N is a natural number of 2 or greater) respectively corresponding to first to N?1th edges among the plurality of edges, a seed calculator configured to calculate an Nth seed corresponding to an Nth edge among the plurality of edges by using the first seed, and a descrambler configured to descramble the scramble data by using the plurality of seeds generated by the linear feedback shift register and the Nth seed calculated by the seed calculator. The linear feedback shift register is further configured to generate an N+1th seed by using the Nth seed.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A calibration circuit, including a duty cycle correction circuit and a phase correction circuit and associated calibrating method, are provided. Firstly, a first duty cycle adjusted clock and a second duty cycle adjusted clock are generated by the duty cycle correction circuit based on a first input clock and a second input clock, respectively. Then, a first delay adjusted clock and a second delay adjusted clock are generated by the phase correction circuit based on a phase of the first duty cycle adjusted clock, and a detection signal is generated. The detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock. Later, the duty cycle correction circuit and the phase correction circuit are controlled in response to the detection signal.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A device for generating restoration data by descrambling scramble data includes a linear feedback shift register configured to receive a first clock including a plurality of edges and sequentially generate a plurality of seeds including first to N?1th seeds (where N is a natural number of 2 or greater) respectively corresponding to first to N?1th edges among the plurality of edges, a seed calculator configured to calculate an Nth seed corresponding to an Nth edge among the plurality of edges by using the first seed, and a descrambler configured to descramble the scramble data by using the plurality of seeds generated by the linear feedback shift register and the Nth seed calculated by the seed calculator. The linear feedback shift register is further configured to generate an N+1th seed by using the Nth seed.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A skew calibration circuit may include a data delay unit receiving first data and a first code, and output delayed first data as second data by delaying the first data according to the first code; a clock delay unit receiving a first clock signal and a second code, and output delayed first clock signal as second clock signal by delaying the first clock signal according to the second code; a multiplexer receiving a clock signal and output the clock signal or an inverted clock signal of the clock signal as a first clock signal in response to a selection signal; and a control logic unit receiving the second data and the second clock signal and control the first code, the second code and the selection signal in response to the second data and the second clock signal.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A skew calibration circuit may include a data delay unit receiving first data and a first code, and output delayed first data as second data by delaying the first data according to the first code; a clock delay unit receiving a first clock signal and a second code, and output delayed first clock signal as second clock signal by delaying the first clock signal according to the second code; a multiplexer receiving a clock signal and output the clock signal or an inverted clock signal of the clock signal as a first clock signal in response to a selection signal; and a control logic unit receiving the second data and the second clock signal and control the first code, the second code and the selection signal in response to the second data and the second clock signal.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A digital duty cycle correction circuit includes a duty cycle controller and a digital duty control code generator. The duty cycle controller generates first and second output clock signals by compensating duty cycles of first and second input clock signals based on a digital duty control code. The digital duty control code generator generates the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal.

Abstract: A frequency compensation apparatus includes a first counter setting a reference period using a main clock, a second counter sensing a change in the frequency of a sub clock using the reference period, and a frequency compensator providing a compensated frequency using information on the changed frequency of the sub clock. Related methods are also described.

Abstract: A data processing device includes a clock converter, a data converter, and an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal. The data converter is configured to receive first data, convert the first data into second data using the second clock signal, and output the second data. The error detector is configured to check whether the first clock signal is in a first clock state or a second clock state upon the first data transitioning to a first data state, and output an enable signal to the clock converter upon determining that the first clock signal has transitioned to the first clock state from the second clock state.