Abstract: A digital duty cycle correction circuit includes a duty cycle controller and a digital duty control code generator. The duty cycle controller generates first and second output clock signals by compensating duty cycles of first and second input clock signals based on a digital duty control code. The digital duty control code generator generates the digital duty control code based on a frequency value obtained by converting duty cycle information of the first output clock signal and the second output clock signal.

Abstract: A frequency compensation apparatus includes a first counter setting a reference period using a main clock, a second counter sensing a change in the frequency of a sub clock using the reference period, and a frequency compensator providing a compensated frequency using information on the changed frequency of the sub clock. Related methods are also described.

Abstract: A data processing device includes a clock converter, a data converter, ad an error detector. The clock converter is configured to receive a first clock signal, convert the first clock signal into a second clock signal, and output the second clock signal. The data converter is configured to receive first data, convert the first data into second data using the second clock signal, and output the second data. The error detector is configured to check whether the first clock signal is in a first clock state or a second clock state upon the first data transitioning to a first data state, and output an enable signal to the clock converter upon determining that the first clock signal has transitioned to the first clock state from the second clock state.

Abstract: A display interface system includes a display transmitter and a display receiver. The display transmitter transmits a control pattern having image type information about a type of an image to be displayed and selectively transmits image data according to the type of the image to be displayed. The display receiver receives the control pattern and selectively receives the image data based upon the image type information, reducing power consumption.

Abstract: A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.

Abstract: A transmission circuit includes a serial clock generator, a serializer and a transmission clock generator. The serial clock generator generates a serial clock. The serializer serializes N-bit parallel data to N-bit serial data in synchronization with the serial clock. The transmission clock generator receives the serial clock to generate a transmission clock that has a same delay as the N-bit serial data, and the data transmission circuit simultaneously transmits the N-bit serial data and the serial clock.

Abstract: A display interface system includes a display transmitter and a display receiver. The display transmitter transmits a control pattern having image type information about a type of an image to be displayed and selectively transmits image data according to the type of the image to be displayed. The display receiver receives the control pattern and selectively receives the image data based upon the image type information, reducing power consumption.

Abstract: A data transmission circuit is disclosed. The transmission circuit includes a serial clock generator, a serializer and a transmission clock generator. The serial clock generator generates a serial clock. The serializer serializes N-bit parallel data to N-bit serial data in synchronization with the serial clock. The transmission clock generator receives the serial clock to generate a transmission clock that has a same delay as the N-bit serial data, and the data transmission circuit simultaneously transmits the N-bit serial data and the serial clock.

Abstract: A deserializer including a plurality of registers, a sync detector, and a lost bit storage unit. If there is a phase difference between an external input data packet and a recovery clock signal transmitted together with the data packet, the sync detector generates an activated sync detect signal. The lost bit storage unit detects a data bit of the data packet corresponding to an activation point of the sync detect signal. The deserializer recovers the data packet by combining the detected data bit with the data packet.