Abstract: An optical sensor includes pixels disposed in a substrate. A light collimating layer is disposed on the substrate and includes a transparent layer, a light-shielding layer, and transparent pillars. The transparent layer blanketly disposed on the substrate covers the pixels and the region between the pixels. The light-shielding layer is disposed on the transparent layer and between the transparent pillars. The transparent pillars penetrating through the light-shielding layer are correspondingly disposed on the pixels.

Abstract: An optical sensor includes a substrate and a light collimating layer. The substrate includes a sensor pixel array having a plurality of sensor pixels. The light collimating layer is disposed on the substrate. The light collimating layer includes a patterned seed layer, a plurality of transparent pillars, a metal layer, and a mask layer. The patterned seed layer is disposed on the substrate. The patterned seed layer exposes the sensor pixel array. The transparent pillars are disposed on the sensor pixel array. The metal layer is disposed on the patterned seed layer and in between the transparent pillars. The mask layer is disposed on the metal layer.

Abstract: An optical sensor is provided, wherein the optical sensor includes an image sensing array, a collimator layer, and a light-shielding layer. The image sensor array includes a plurality of pixels. The collimator layer is disposed on the image sensor array and includes a plurality of openings corresponding to the pixels. The collimator layer includes a first surface facing the image sensor array and a second surface opposite to the first surface. The light-shielding layer is disposed on sidewalls of the openings.

Abstract: An optical sensor structure is provided. The optical sensor structure includes a sensor pixel array in a substrate, a light collimating layer on the substrate, and at least one through-substrate via. The sensor pixel array has a plurality of sensor pixels. The at least one through-substrate via extends from a first surface to an opposite second surface of the substrate. The at least one through-substrate via is in the sensor pixel array and vertically misaligned with the plurality of sensor pixels.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a substrate, forming a first light-shielding layer on the substrate, and performing a first lithography process to pattern the first light-shielding layer to form a plurality of first openings in the first light-shielding layer. The first openings expose pixels of the substrate. The method also includes placing a first stencil on the first light-shielding layer. The first stencil has a first openwork pattern which exposes the pixels of the substrate. The method also includes providing a first material. The first material includes a transparent material. The method also includes applying the first material onto the substrate through the first stencil to cover the pixels and fill the first openings, such that a plurality of first transparent pillars made of the first material are formed on the pixels.

Abstract: An optical sensor is provided, wherein the optical sensor includes an image sensing array, a collimator layer, and a light-shielding layer. The image sensor array includes a plurality of pixels. The collimator layer is disposed on the image sensor array and includes a plurality of openings corresponding to the pixels. The collimator layer includes a first surface facing the image sensor array and a second surface opposite to the first surface. The light-shielding layer is disposed on sidewalls of the openings.

Abstract: A method for forming a semiconductor device is provided. The method includes providing a substrate, placing a first stencil having a first openwork pattern on the substrate, applying a first material onto the substrate through the first stencil, and removing the first stencil from the substrate. The first material includes a transparent material. The method also includes placing a second stencil having a second openwork pattern on the substrate, applying a second material onto the substrate through the second stencil, and removing the second stencil from the substrate. The second material includes a light-shielding material, and the second openwork pattern is different from the first openwork pattern.

Abstract: A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip.

Abstract: A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate.

Abstract: A chip holder formed of silicon, glass, other ceramics or other suitable materials includes a plurality of recesses for retaining semiconductor chips. The bond pads of the semiconductor chip are formed on or over an area of the chip holder that surrounds the semiconductor chip thus expanding the bonding area. The bond pads are coupled, using semiconductor wafer processing techniques, to internal bond pads formed directly on the semiconductor chip.

Abstract: A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate.

Abstract: A method for measuring a dielectric layer thickness calibration reference standard including providing a substrate having a dielectric layer for calibrating a dielectric layer thickness measuring tool; cleaning the dielectric layer according to a cleaning process including at least one of spraying and scrubbing; and, measuring the thickness of the dielectric layer with the dielectric layer thickness measuring tool including at least one portion of the dielectric layer displaced from the substrate center.

Abstract: A method for measuring a dielectric layer thickness calibration reference standard including providing a substrate having a dielectric layer for calibrating a dielectric layer thickness measuring tool; cleaning the dielectric layer according to a cleaning process including at least one of spraying and scrubbing; and, measuring the thickness of the dielectric layer with the dielectric layer thickness measuring tool including at least one portion of the dielectric layer displaced from the substrate center.

Abstract: A method and apparatus comprising a wafer platform which rotates a semiconductor wafer at a predetermined speed while being moved in a linear motion with respect to a stationary water jet nozzle spraying a water or fluid jet onto the wafer during a wafer scrubbing process. The coupled rotary and linear motions of the wafer facilitates through washing or rinsing of the wafer surface and spreads impact energy of water or fluid sprayed onto a wafer surface over a large surface area on the wafer, resulting in a substantial reduction of particles remaining at the center of the wafer after the wafer scrubbing operation and preventing or minimizing the likelihood of impact damage to the wafer during the wafer scrubbing process. In another embodiment, the water or fluid jet nozzle moves along a horizontal axis while the spinning wafer remains stationary.

Abstract: A method is described for forming trench isolation for integrated circuits on silicon wafers by selectively doping the trench regions by ion implantation and then etching these areas with a wet chemical etch. A dopant such as boron, is implanted in a sequence of energies and doses to provide a desired trench profile of heavily doped silicon. The implanted silicon etches far more rapidly than the surrounding silicon and is readily etched out forming a trench. The concentration of dopant diminishes rapidly in the periphery of the implanted region. As the etch front approaches the periphery, the silicon etch rate, likewise diminishes and the etch can be quenched to leave a uniform surface layer of enhanced boron concentration which lines the resultant trench to form an effective channel stop. Wet etched trenches provide advantages over trenches formed by RIE including smooth rounded trench profiles which reduce stress. In addition, trenches having widths below 0.

Abstract: A process is described for forming a microlens, either directly on a substrate or as part of a process to manufacture an optical imaging array. The process starts with the deposition of a layer of silicon oxide over the substrate, said layer being the determinant of the lens to substrate distance. This is followed by layers of polysilicon and silicon nitride. The latter is patterned to form a mask which protects the poly, except for a small circular opening, during its oxidation (under the same conditions as used for LOCOS). The oxide body that is formed is lens shaped, extending above the poly surface by about the same amount as below it, and just contacting the oxide layer. After the silicon nitride and all poly have been removed, the result is a biconvex microlens. In a second embodiment, a coating of SOG is provided that has a thickness equal to half the microlens thickness, thereby converting the latter to a plano-convex lens.

Abstract: An integrated de-focus pattern provides an effective in-line monitor for photo processing steps of integrated circuit wafers. The de-focus pattern is formed on an integrated circuit wafer in the vertical and horizontal spaces between integrated circuit chips. The de-focus pattern has a number of different test patterns at different heights above the wafer surface. De-focus patterns are placed across the entire wafer surface. The de-focus patterns are formed at the same time the features of the circuit chips are formed. The de-focus patterns can be analyzed optically or using a scanning electron microscope.

Abstract: An integrated de-focus pattern provides an effective in-line monitor of de-focus and relative tilt for photo processing steps of integrated circuit wafers. The de-focus pattern is formed on an integrated circuit wafer in the vertical and horizontal spaces between integrated circuit chips. The de-focus pattern has a number of different test patterns at different heights above the wafer surface. De-focus patterns are placed across the entire wafer surface. The de-focus patterns are formed at the same time the features of the circuit chips are formed. The de-focus patterns can be analyzed optically or using a scanning electron microscope.

Abstract: A polysilicon resistor structure and a method by which the polysilicon resistor structure may be formed. A polysilicon resistor is formed upon the surface of a semiconductor substrate. A pair of dummy polysilicon layers is formed along opposite edges and separated from the polysilicon resistor. A pair of metal sidewalls is then formed upon the upper surfaces of the pair of dummy polysilicon layers, and a top metal layer is formed bridging the upper surfaces of the pair of metal sidewalls. The pair of dummy polysilicon layers, the pair of metal sidewalls and the top metal layer form an open ended cavity upon the semiconductor substrate within which structure the polysilicon resistor resides. The polysilicon resistor is separated from the structure by an insulating material which is not susceptible to outgassing of hydrogen.