Abstract: A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.

Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Abstract: The present disclosure, in some embodiments, relates to a transistor device within an active area having a shape configured to reduce a susceptibility of the transistor device to performance degradation (e.g., the kink effect) caused by divots in an adjacent isolation structure. The transistor device has a substrate including interior surfaces defining a trench within an upper surface of the substrate. One or more dielectric materials are arranged within the trench. The one or more dielectric materials define an opening exposing the upper surface of the substrate. The opening has a source opening over a source region within the substrate, a drain opening over a drain region within the substrate, and a channel opening between the source opening and the drain opening. The source opening and the drain opening have widths smaller than the channel opening. A gate structure extends over the opening between the source and drain regions.

Abstract: A frameless panel light includes a light source module and a lamp cover having a front portion and side portions surrounding the front portion. The front and side portions define an accommodating space. The light source module is disposed in the accommodating space and includes a light source and a light guide plate. The light guide plate includes a light-transmissive substrate including first and second major surfaces and a side surface connecting the first and second major surfaces and a microstructure formed on the first major surface and including a recess and an annular groove around the recess. The annular groove has a depth greater than that of the recess. A bottom of the recess is at higher elevation than the first major surface from the second major surface. The annular groove has a protruding portion protruding from a bottom of the annular groove.

Abstract: Examples of an integrated circuit and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a substrate that includes: a plurality of fins extending above a remainder of the substrate; a first region that includes a first fence region that contains a first subset of the plurality of fins; and a second region that includes a second fence region that contains a second subset of the plurality of fins. The first region has a first performance characteristic, and the second region has a second performance characteristic that is different from the first. Based on the first performance characteristic, the first subset of the plurality of fins is recessed to a first height, and based on the second performance characteristic, the second subset of the plurality of fins is recessed to a second height that is less than the first height.

Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.

Abstract: A method for transferring a container for holding one or more articles is provided. The method includes transferring the container using a transferring mechanism to a position which is adjacent to a destination space. The method further includes recording an image of the destination space before the container is deposited to the destination space. The method also includes performing an image analysis of the image and determining if the container is able to be sent to the destination space according to a result of the image analysis of the image.

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex machine learning compute operation.

Abstract: Detailed herein are embodiments of systems, methods, and apparatuses to be used for feature searching using an entry-based searching structure.

Abstract: A method of forming a semiconductor device includes receiving a device having a substrate and a first dielectric layer surrounding a gate trench. The method further includes depositing a gate dielectric layer and a gate work function (WF) layer in the gate trench, and forming a hard mask (HM) layer in a space surrounded by the gate WF layer. The method further includes recessing the gate WF layer such that a top surface of the gate WF layer in the gate trench is below a top surface of the first dielectric layer. After the recessing of the gate WF layer, the method further includes removing the HM layer in the gate trench. After the removing of the HM layer, the method further includes depositing a metal layer in the gate trench.

Abstract: Contact structures, FinFET devices and methods of forming the same are disclosed. One of the contact structures includes a source/drain region, a mask layer, a connector and a shielding pattern. The source/drain region is between two gate stacks. A mask layer is over the gate stacks and has an opening corresponding to the source/drain region. The connector is electrically connected to the source/drain region, penetrates through the opening of the mask layer and protrudes above and below the mask layer. The shielding pattern is between the mask layer and the connector and in physical contact with the mask layer.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack and a second gate stack over a substrate. Each of them has gate spacers disposed along its respective sidewalls. The method also includes forming a source/drain (S/D) feature disposed between the first and second gate stacks. The gate spacers and a top surface of the S/D feature define a space. The method also includes forming a first dielectric layer over the S/D feature in the space, forming a capping layer along the gate spacers in the space, forming a second dielectric layer over the first dielectric layer in the space and forming a contact trench extending through the second dielectric layer, the first dielectric layer and the capping layer to expose the top surface of the S/D feature.

Abstract: Bridging testing method between adjacent semiconductor devices includes forming patterned diffusion region on semiconductor substrate, and forming first conductive layer over diffusion region. First conductive layer is patterned in same pattern as patterned diffusion region. Second conductive layer formed extending in first direction over first conductive layer. Second conductive layer is patterned to form opening extending in first direction in central region of second conductive layer exposing portion of first conductive layer. First conductive layer exposed portion is removed exposing portion of diffusion region. Source/drain region is formed over exposed portion of diffusion region, and dielectric layer is formed over source/drain region. Third conductive layer is formed over dielectric layer. End portions along first direction of second conductive layer removed to expose first and second end portions of first conductive layer.

Abstract: A method for manufacturing a semiconductor device includes forming first and second fins over a substrate, forming first and second dummy gate structures over the first and second fins, respectively, replacing the first and second dummy gate structures with first and second gate structures, respectively, and after replacing the first and second dummy gate structures, forming an insulating structure between the first and second gate structures.

Abstract: A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.

Abstract: A light guide plate includes a light-transmissive substrate and at least one microstructure. The light-transmissive substrate includes first and second major surfaces and a side surface connecting the first and second major surfaces. The microstructure is formed on the first major surface. The microstructure comprises a recess and an annular groove around the recess. The annular groove has a depth greater than a depth of the recess. A bottom of the recess is at higher elevation than the first major surface from the second major surface.

Abstract: A method of forming a semiconductor device includes receiving a substrate having a fin extending from the substrate, first and second dummy gate stacks over the substrate and engaging the fin; removing the first and second dummy gate stacks thereby forming a first trench and a second trench, wherein the first and second trenches expose first and second portions of the fin respectively; removing the first portion of the fin; and forming a gate stack in the second trench, the gate stack engaging the second portion of the fin.

Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-? dielectric layer and a gate electrode. The high-? dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-? dielectric layer.

Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a patterned mask stack over a substrate, features of the patterned mask stack protecting the substrate having a uniform width. Unprotected portions of the substrate exposed by the patterned mask stack are removed to form a plurality of recesses in the substrate, unremoved portions of the substrate interposed between adjacent recesses forming a plurality of fins. Portions of the plurality of fins are removed, a width of a first fin of the plurality of fins being less than a width of a second fin of the plurality of fins.

Abstract: An embodiment method includes forming first dummy gate stack and a second dummy gate stack over a semiconductor fin. A portion of the semiconductor fin is exposed by an opening between the first dummy gate stack and the second dummy gate stack. The method further includes etching the portion of the semiconductor fin to extend the opening into the semiconductor fin. A material of the semiconductor fin encircles the opening in a top-down view of the semiconductor fin. The method further includes epitaxially growing a source/drain region in the opening on the portion of the semiconductor fin.