Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a gate dielectric layer, a work function layer, and a conductive filling over the work function layer. The semiconductor device structure also includes a dielectric layer covering the fin structure. The dielectric layer is in direct contact with the conductive filling.

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.

Abstract: An image sensing device is provided. The image sensing device includes a substrate having a pixel array with a plurality of pixels. A light guide structure is disposed over the substrate, forming a plurality of light pipes and a plurality of reflecting portions surrounding the light pipes. The light pipes are aligned with the pixels of the pixel array. The invention also provides a method for fabricating the image sensing device.

Abstract: A solid-state imaging device has a sensing region, a pad region and a peripheral region between the sensing region and the pad region. The solid-state imaging device includes a plurality of photoelectric conversion elements formed in a semiconductor substrate and disposed in the sensing region, and a bond pad disposed on the semiconductor substrate and in the pad region. The solid-state imaging device further includes a microlens layer disposed above the semiconductor substrate. The microlens layer includes a microlens array in the sensing region and a first dummy structure in the pad region. The first dummy structure includes a plurality of first microlens elements disposed to surround an area of the bond pad. Moreover, the solid-state imaging device includes a passivation film conformally formed on a top surface of the microlens layer.

Abstract: Described are methods of depositing a titanium aluminum nitride film on a substrate surface with a controlled amount of carbon. The methods include exposing a substrate surface to a titanium precursor, a nitrogen reactant and an aluminum precursor with purges of the unreacted titanium and aluminum precursors and unreacted nitrogen reactants between each exposure.

Abstract: A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of depositing a first insulating material over a substrate, and forming a first conductive contact in the first insulating material. The first conductive contact has a protruding uppermost surface, with a first height along a central portion of the first conductive contact, and a second height along a vertical vector projection of a sidewall of the first conductive contact. The first height is larger than the second height. A second insulating material is deposited over the first insulating material, and a second conductive contact is formed in the second insulating material. The second conductive contact is disposed over and at least partially within the first conductive contact. A distance between a bottommost surface of the second conductive contact and the protruding uppermost surface of the first conductive contact is less than about 1.0 nm.

Abstract: The invention relates to a methods for detecting RNA sequences. The invention also relates to nucleotide sequences, primers, probes and microarrays.

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

Abstract: Disclosed is an electromagnetic vibratory pump, comprising a first C-shaped winding and a first magnet. The first C-shaped winding comprises a first coil and a first electromagnetizable member. The first coil covers the first electromagnetizable member, which comprises a first main body, a first leg and a second leg. The legs are connected to the first main body, and the distance between the legs is reduced from a first width to a second width from the first main body. The first magnet swings in a circular tangential direction. A point of tangency of the circular tangential direction is configured apart from the first leg and the second leg respectively by a first minimum distance. The first minimum distance is less than a half of the second width. The first magnet is driven by the first magnetic line of force to move in the first circular tangential direction, and the first magnet is driven by the second magnetic line of force to move in the second circular tangential direction.

Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductive plug, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure. The protection layer is present between the conductive plug and the spacer.

Abstract: A semiconductor device includes a substrate; first and second fins over the substrate and extending lengthwise generally along a first direction; first and second gate stacks over the substrate and the first and second fins respectively; and a first isolation structure disposed between the first and second fins and extending lengthwise generally along a second direction perpendicular to the first direction, wherein the first isolation structure is adjacent to a first source/drain (S/D) region in the first fin and adjacent to a second S/D region in the second fin.

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.

Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-? dielectric layer and a gate electrode. The high-? dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-? dielectric layer.

Abstract: A method of forming a gate isolation plug for FinFETs includes forming an elongated gate, forming first and second spacers in contact with first and second sidewalls of the elongated gate, separating the elongated gate into first and second gate portions using first and second etching steps, and forming a gate isolation plug between the first and second gate portions, wherein a length of the gate isolation plug is greater than a length of either of the first or second gate portions.

Abstract: A method of forming a semiconductor device includes receiving a substrate with a plurality of gate structures; forming spacers on sidewalls of the gate structures; evaluating a pitch variation to the gate structures; determining an etch recipe according to the pitch variation; performing an etch process to source/drain regions associated with the gate structures using the etch recipe, thereby forming source/drain recesses with respective depths; and performing an epitaxy growth to form source/drain features in the source/drain recesses using a semiconductor material.

Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.

Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a second conductive via and an etch stop layer. The first conductive via and the second conductive via are respectively disposed in the first dielectric layer. The etch stop layer is disposed on the first dielectric layer and contacts the first and second conductive vias. The etch stop layer includes nitrogen-and-oxygen-doped silicon carbide (NODC).

Abstract: A semiconductor device and method of manufacture are provided. A source/drain region is formed next to a spacer, which is adjacent to a gate electrode. An implantation is performed through an implantation mask into the source/drain region as well as the first spacer, forming an implantation region within the spacer.

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.