Patents by Inventor Han-Shin Youn

Han-Shin Youn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190248242
    Abstract: A fault diagnosis system of a power converter for an electric vehicle includes a power supply supplied with power and converting the supplied power to provide the power to a motor, a battery, and an electronic device of a vehicle, a power supply supplied with power and converting the supplied power to provide the power to a motor, a battery, and an electronic device of a vehicle, a controller connected to the power supply by a connector and controlling charging and discharging of the battery, and operations of the motor and the electronic device of the vehicle by using the power provided from the power supply, and a fault diagnosis circuit connected between the power supply and the controller and diagnosing whether the connector which connects the power supply with the controller malfunctions.
    Type: Application
    Filed: July 24, 2018
    Publication date: August 15, 2019
    Inventors: Han Shin YOUN, Ho Joong LEE, Jee Heon KIM, Dong Jun LEE, Hye Seung KIM
  • Publication number: 20190184838
    Abstract: A method of controlling a vehicle during charging is applied to the vehicle that includes a charger converting external alternating current power into direct current power, and a first battery and an electric load connected to a terminal to which the direct current power converted and output by the charger. The method includes calculating a maximum outputtable power capable of being output by the charger when an operation of the charger is initiated; and calculating a maximum allowable load power capable of being applied to drive the electric load on the basis of the maximum outputtable power, a minimum charging power required to charge the first battery, and a minimum load-requesting power required to operate the electric load.
    Type: Application
    Filed: June 8, 2018
    Publication date: June 20, 2019
    Inventors: Ho Joong Lee, Han Shin Youn, Jee Heon Kim, Dong Jun Lee, Hye Seung Kim
  • Publication number: 20190190285
    Abstract: A charging system with a sensor diagnosis function is provided. The system includes an AC input voltage sensor that detects a voltage of an input end with an AC power applied thereto and a resistor that is connected to the input end. A power factor correction circuit unit adjusts and outputs a power factor of AC power applied through the resistor. An output voltage of the power factor correction circuit unit is applied to a capacity of the system. A controller then diagnoses the AC input voltage sensor based on a value of current passing through the resistor, a value of a voltage of the capacitor, and a resistance value of the resistor.
    Type: Application
    Filed: June 1, 2018
    Publication date: June 20, 2019
    Inventors: Ho Joong Lee, Han Shin Youn, Jee Heon Kim, Dong Jun Lee, Hye Seung Kim
  • Patent number: 9866130
    Abstract: A DC-DC converter includes: a clamp capacitor having one terminal connected with a ground terminal of a voltage source; a switching circuit including first and second switches connected with each other in series between a positive terminal and the ground terminal of the voltage source, and third and fourth switches connected with each other in series between both terminals of the clamp capacitor; and a forward-flyback transformer including a plurality of primary coils connected between a first connection node between the first and second switches and a second connection node between the third and fourth switches.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: January 9, 2018
    Assignees: Hyundai Motor Company, Kia Motors Corporation, Korea Advanced Institute of Science and Technology
    Inventors: Jaehyuk Choi, Woo Young Lee, Seok Joon Kim, Jong Pil Kim, Sam Gyun Kim, Gun Woo Moon, Han Shin Youn, Jae Bum Lee, Jae Il Baek
  • Patent number: 9018041
    Abstract: An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad. At least one electrode is coupled between the first pad and the second pad. The semiconductor package includes a guide ring formed at a periphery of the electrode between the first substrate and the second substrate.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: April 28, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-shin Youn, Yonghwan Kwon, YoungHoon Ro, Woojae Kim, Sungwoo Park
  • Publication number: 20140051243
    Abstract: An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad. At least one electrode is coupled between the first pad and the second pad. The semiconductor package includes a guide ring formed at a periphery of the electrode between the first substrate and the second substrate.
    Type: Application
    Filed: October 28, 2013
    Publication date: February 20, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Han-shin YOUN, Yonghwan KWON, YoungHoon RO, Woojae KIM, Sungwoo PARK
  • Publication number: 20130234310
    Abstract: A flip chip package may include package substrate, a semiconductor chip, conductive bumps, a molding member and a heat sink. The semiconductor chip may be arranged over an upper surface of the package substrate. The conductive bumps may be interposed between a lower surface of the semiconductor chip and the upper surface of the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The molding member may be formed on the upper surface of the package substrate to cover the semiconductor chip. The heat sink may make contact with the semiconductor chip to dissipate a heat in the semiconductor chip. An ultrasonic wave may pass through only one interface between the semiconductor chip and the molding member, so that scattering of the ultrasonic wave may be suppressed.
    Type: Application
    Filed: October 15, 2012
    Publication date: September 12, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han-Shin Youn, Kyong-Soon Cho
  • Patent number: 8278154
    Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: October 2, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Shin Youn, Young-Shin Kwon
  • Patent number: 8124459
    Abstract: A bump chip carrier semiconductor package system is provided including providing a lead frame, forming circuit sockets in the lead frame, mounting a semiconductor die on the lead frame, wherein the semiconductor die have electrical interconnects that connects to the circuit sockets, and encapsulating a molding compound to cover the semiconductor die and the electrical interconnects.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: February 28, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: In Sang Yoon, Han Shin Youn, Jae Soo Lee
  • Publication number: 20120040498
    Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.
    Type: Application
    Filed: October 21, 2011
    Publication date: February 16, 2012
    Applicant: Samsung Electronics Co., Ltd
    Inventors: Han-Shin YOUN, Young-Shin Kwon
  • Patent number: 7952199
    Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Gui Jo, Seung-Kon Mok, Han-Shin Youn
  • Publication number: 20100116539
    Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.
    Type: Application
    Filed: January 8, 2010
    Publication date: May 13, 2010
    Inventors: Sang-Gui Jo, Seung-Kon Mok, Han-Shin Youn
  • Patent number: 7667325
    Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: February 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Gui Jo, Seung-Kon Mok, Han-Shin Youn
  • Publication number: 20100019372
    Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.
    Type: Application
    Filed: July 23, 2009
    Publication date: January 28, 2010
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Han-Shin YOUN, Young-Shin Kwon
  • Patent number: 7504736
    Abstract: A semiconductor packaging mold includes first and second mold bodies, a cavity defined by the first and second mold bodies to provide a space for molding a semiconductor package, and a resin bleed preventing formation on a cavity surface of one of the first and second mold bodies to suppress resin bleeding.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: March 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Uk Kim, Han-Shin Youn
  • Patent number: 7436049
    Abstract: A semiconductor chip package with a lead frame having a plurality of leads formed along four sides of the lead frame and tie bars extending from an edge of each of the four sides, wherein bottom surfaces of the tie bars are recessed, a semiconductor chip which is adhered to the recessed surfaces of the tie bars, connectors which electrically connect a plurality of chip pads formed on an upper surface of the semiconductor chip with the plurality of leads, and an encapsulant which encapsulates the upper surface of the semiconductor chip, the connector and bonding portions of the connector.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: October 14, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Shin Youn, Hyun-Ki Kim
  • Publication number: 20080036085
    Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.
    Type: Application
    Filed: May 7, 2007
    Publication date: February 14, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Gui JO, Seung-Kon MOK, Han-Shin YOUN
  • Publication number: 20070190688
    Abstract: A method for manufacturing a semiconductor device may comprise preparing a wafer having a front surface and a back surface. The wafer may have a plurality of semiconductor chips and scribe lines between the adjacent semiconductor chips. The wafer may be sawn along the scribe lines to form grooves between the adjacent semiconductor chips. A liquid protection material may be screen printed or spin-coated to form a protection layer on the back surface and within the grooves. The protection layer within the grooves may be more narrowly cut to form individual semiconductor devices and to leave a protection layer remaining thereon.
    Type: Application
    Filed: December 1, 2006
    Publication date: August 16, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han-Shin YOUN, Seung-Kon MOK, Young-Doo JUNG
  • Publication number: 20070108605
    Abstract: A bump chip carrier semiconductor package system is provided including providing a lead frame, forming circuit sockets in the lead frame, mounting a semiconductor die on the lead frame, wherein the semiconductor die have electrical interconnects that connects to the circuit sockets, and encapsulating a molding compound to cover the semiconductor die and the electrical interconnects.
    Type: Application
    Filed: January 11, 2006
    Publication date: May 17, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: In Sang Yoon, Han Shin Youn, Jae Soo Lee
  • Publication number: 20060214283
    Abstract: A semiconductor packaging mold includes first and second mold bodies, a cavity defined by the first and second mold bodies to provide a space for molding a semiconductor package, and a resin bleed preventing formation on a cavity surface of one of the first and second mold bodies to suppress resin bleeding.
    Type: Application
    Filed: March 28, 2006
    Publication date: September 28, 2006
    Inventors: Sang-Uk Kim, Han-Shin Youn