Abstract: A DC-DC converter includes: a clamp capacitor having one terminal connected with a ground terminal of a voltage source; a switching circuit including first and second switches connected with each other in series between a positive terminal and the ground terminal of the voltage source, and third and fourth switches connected with each other in series between both terminals of the clamp capacitor; and a forward-flyback transformer including a plurality of primary coils connected between a first connection node between the first and second switches and a second connection node between the third and fourth switches.

Abstract: An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad. At least one electrode is coupled between the first pad and the second pad. The semiconductor package includes a guide ring formed at a periphery of the electrode between the first substrate and the second substrate.

Abstract: An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad. At least one electrode is coupled between the first pad and the second pad. The semiconductor package includes a guide ring formed at a periphery of the electrode between the first substrate and the second substrate.

Abstract: A flip chip package may include package substrate, a semiconductor chip, conductive bumps, a molding member and a heat sink. The semiconductor chip may be arranged over an upper surface of the package substrate. The conductive bumps may be interposed between a lower surface of the semiconductor chip and the upper surface of the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The molding member may be formed on the upper surface of the package substrate to cover the semiconductor chip. The heat sink may make contact with the semiconductor chip to dissipate a heat in the semiconductor chip. An ultrasonic wave may pass through only one interface between the semiconductor chip and the molding member, so that scattering of the ultrasonic wave may be suppressed.

Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.

Abstract: A bump chip carrier semiconductor package system is provided including providing a lead frame, forming circuit sockets in the lead frame, mounting a semiconductor die on the lead frame, wherein the semiconductor die have electrical interconnects that connects to the circuit sockets, and encapsulating a molding compound to cover the semiconductor die and the electrical interconnects.

Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.

Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.

Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.

Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.

Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.

Abstract: A semiconductor packaging mold includes first and second mold bodies, a cavity defined by the first and second mold bodies to provide a space for molding a semiconductor package, and a resin bleed preventing formation on a cavity surface of one of the first and second mold bodies to suppress resin bleeding.

Abstract: A semiconductor chip package with a lead frame having a plurality of leads formed along four sides of the lead frame and tie bars extending from an edge of each of the four sides, wherein bottom surfaces of the tie bars are recessed, a semiconductor chip which is adhered to the recessed surfaces of the tie bars, connectors which electrically connect a plurality of chip pads formed on an upper surface of the semiconductor chip with the plurality of leads, and an encapsulant which encapsulates the upper surface of the semiconductor chip, the connector and bonding portions of the connector.

Abstract: A circuit board and a semiconductor package having the same are provided. The circuit board comprises a base substrate having interconnections, and solder ball lands disposed on one surface of the base substrate. The solder ball lands respectively have land holes having different sizes. The land hole disposed at the center portion of the base substrate and the land hole disposed at the edge portion of the base substrate may have different sizes. For example, the sizes of the land holes may increase from the center portion of the base substrate to the edge portion thereof, and alternatively, the sizes of the land holes may decrease from the center portion of the base substrate to the edge portion thereof.

Abstract: A method for manufacturing a semiconductor device may comprise preparing a wafer having a front surface and a back surface. The wafer may have a plurality of semiconductor chips and scribe lines between the adjacent semiconductor chips. The wafer may be sawn along the scribe lines to form grooves between the adjacent semiconductor chips. A liquid protection material may be screen printed or spin-coated to form a protection layer on the back surface and within the grooves. The protection layer within the grooves may be more narrowly cut to form individual semiconductor devices and to leave a protection layer remaining thereon.

Abstract: A bump chip carrier semiconductor package system is provided including providing a lead frame, forming circuit sockets in the lead frame, mounting a semiconductor die on the lead frame, wherein the semiconductor die have electrical interconnects that connects to the circuit sockets, and encapsulating a molding compound to cover the semiconductor die and the electrical interconnects.

Abstract: A semiconductor packaging mold includes first and second mold bodies, a cavity defined by the first and second mold bodies to provide a space for molding a semiconductor package, and a resin bleed preventing formation on a cavity surface of one of the first and second mold bodies to suppress resin bleeding.

Abstract: A flip chip bonding structure has a non-conductive adhesive interposed between an integrated circuit (IC) chip and a circuit substrate. The IC chip has I/O pads on an active surface thereof, and the circuit substrate has bump pads on a first surface thereof. The non-conductive adhesive is provided on the active surface of the chip or alternatively on the first surface of the substrate, exposing the I/O pads or the bump pads respectively. Conductive bumps such as metal bumps are formed on the I/O pads and then bonded to the bump pads. With no adhesive between the metal bumps and the bump pads, non-conductive particles in the adhesive do not obstruct mechanical and electrical connections therebetween. The particle content of the non-conductive adhesive can be increased and flip chip bonding structures can be formed in a wafer level process.

Abstract: A semiconductor chip package with a lead frame having a plurality of leads formed along four sides of the lead frame and tie bars extending from an edge of each of the four sides, wherein bottom surfaces of the tie bars are recessed, a semiconductor chip which is adhered to the recessed surfaces of the tie bars, connectors which electrically connect a plurality of chip pads formed on an upper surface of the semiconductor chip with the plurality of leads, and an encapsulant which encapsulates the upper surface of the semiconductor chip, the connector and bonding portions of the connector.

Abstract: Disclosed is a packaged integrated circuit device with high heat dissipation performance and low weight. The packaged integrated circuit device includes an interconnection substrate having at least one layer of conductive trace material and at least one layer of insulating material and also having a first surface and a second surface disposed opposite to the first surface and having a plurality of electrical contacts formed on the second surface. At least one metal thermal conductive layer having a first surface is attached on the first surface of the interconnection substrate and having a second surface exposed to an exterior. A through hole region is formed in the interconnection substrate and the thermal conductive layer. An integrated circuit chip having a first surface exposed to an exterior and having also a second surface with a plurality of bond pads, opposite to the first surface of the integrated circuit chip, is placed within the through hole region.