Patents by Inventor Han Sung Chen
Han Sung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240071523Abstract: A memory device and a programming method thereof are provided. The programming method includes the following steps. According to a step value, based on an incremental step pulse programming scheme, multiple programming operations are performed for a selected memory page. In a setting mode, multiple program verify operations are respectively performed corresponding to the programming operations to respectively generate multiple pass bit numbers. In the setting mode, a pass bit number difference value of two pass bit numbers corresponding to two programming operations is calculated. In the setting mode, an amount of the step value is adjusted according to the pass bit number difference value.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: MACRONIX International Co., Ltd.Inventors: Kun-Tse Lee, Han-Sung Chen, Shih-Chang Huang
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Patent number: 11488657Abstract: A memory having a plurality of blocks is coupled with control circuits having logic to execute a no-current read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks while disabling current flow. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include, respectively, a plurality of sub-blocks. The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.Type: GrantFiled: April 19, 2021Date of Patent: November 1, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Jen-Hung Huang, Han-Sung Chen
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Publication number: 20220336006Abstract: A memory having a plurality of blocks is coupled with control circuits having logic to execute a no-current read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks while disabling current flow. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include, respectively, a plurality of sub-blocks. The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.Type: ApplicationFiled: April 19, 2021Publication date: October 20, 2022Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Jen-Hung HUANG, Han-Sung CHEN
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Patent number: 11475954Abstract: A memory having a plurality of blocks is coupled with control circuits having logic to execute a read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include respectively a plurality of sub-blocks, The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.Type: GrantFiled: January 20, 2021Date of Patent: October 18, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Han-Sung Chen, Chung-Kuang Chen
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Publication number: 20220157379Abstract: A memory having a plurality of blocks is coupled with control circuits having logic to execute a read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include respectively a plurality of sub-blocks, The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.Type: ApplicationFiled: January 20, 2021Publication date: May 19, 2022Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Han-Sung CHEN, Chung-Kuang CHEN
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Patent number: 11282581Abstract: A memory device has a plurality of blocks of memory cells and a plurality of bit lines, each block including a group of word lines, and a set of NAND strings. Each block in the plurality of blocks of memory cells has a plurality of sub-blocks, each sub-block including a distinct subset of the set of NAND strings of the block selected, and a respective sub-block string select line. Control circuits are configured to execute a program operation including applying word line voltages and string select line voltages at a precharge level to precharge the set of NAND strings in the selected block, then lowering the gate voltages on all the sub-block string select lines of the block, and then lowering the word line voltages on the group of word lines. Thereafter, the program of cells in a selected sub-block is executed.Type: GrantFiled: January 4, 2021Date of Patent: March 22, 2022Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Han-Sung Chen, Chien-Fu Huang
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Patent number: 10790009Abstract: A memory device comprises a memory cell array, a plurality of sense amplifiers and a memory controller for controlling the plurality of sense amplifiers. The memory cell array includes a plurality of bit lines, where a bit line is coupled to a plurality of memory cells. A sense amplifier is coupled to a bit line and provides a sensing current to access data from one or more memory cells of the plurality of memory cells corresponding to the bit line. The memory controller performs operations comprising: during a pre-charging stage of a memory access cycle, providing, to a particular sense amplifier, a first voltage; and during a sensing stage of the memory access cycle, providing, to the particular sense amplifier, a second voltage, where the second voltage is a non-zero voltage that is lower than the first voltage.Type: GrantFiled: August 27, 2019Date of Patent: September 29, 2020Assignee: Macronix International Co., Ltd.Inventors: Chung-Kuang Chen, Han-Sung Chen
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Patent number: 10650887Abstract: A first read operation is performed using a first voltage level to read data from a memory array. An instant bit count corresponding to a number of bits in the data read from the memory array is determined. A recorded bit count corresponding to a number of bits in the data that was written at a time of writing the data to the memory array is accessed. A difference between the instant bit count and the recorded bit count is obtained. Conditioned on determining that the difference is less than or equal to a first threshold value, the data read from the memory array is output using the first read operation. Conditioned on determining that the difference is greater than the first threshold value, a second read operation is performed using a second voltage level that is distinct from the first voltage level.Type: GrantFiled: April 20, 2018Date of Patent: May 12, 2020Assignee: Macronix International Co., Ltd.Inventors: Chun Hsiung Hung, Han Sung Chen, Ming Chao Lin
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Patent number: 10637476Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.Type: GrantFiled: December 29, 2017Date of Patent: April 28, 2020Assignee: Macronix International Co., Ltd.Inventors: Chung-Kuang Chen, Chun Hsiung Hung, Han Sung Chen
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Publication number: 20180240518Abstract: A first read operation is performed using a first voltage level to read data from a memory array. An instant bit count corresponding to a number of bits in the data read from the memory array is determined. A recorded bit count corresponding to a number of bits in the data that was written at a time of writing the data to the memory array is accessed. A difference between the instant bit count and the recorded bit count is obtained. Conditioned on determining that the difference is less than or equal to a first threshold value, the data read from the memory array is output using the first read operation. Conditioned on determining that the difference is greater than the first threshold value, a second read operation is performed using a second voltage level that is distinct from the first voltage level.Type: ApplicationFiled: April 20, 2018Publication date: August 23, 2018Applicant: Macronix International Co., Ltd.Inventors: Chun Hsiung Hung, Han Sung Chen, Ming Chao Lin
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Patent number: 9977627Abstract: A memory device includes a memory unit including a plurality of memory cells, and a controller including a storage unit that stores a plurality of operation selections each corresponding to a property of at least one selected memory cell among the plurality of memory cells.Type: GrantFiled: November 9, 2016Date of Patent: May 22, 2018Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Han-Sung Chen, Chung-Kuang Chen
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Patent number: 9972383Abstract: A first read operation is performed using a first voltage level to read data from a memory array. An instant bit count corresponding to a number of bits in the data read from the memory array is determined. A recorded bit count corresponding to a number of bits in the data that was written at a time of writing the data to the memory array is accessed. A difference between the instant bit count and the recorded bit count is obtained. Conditioned on determining that the difference is less than or equal to a first threshold value, the data read from the memory array is output using the first read operation. Conditioned on determining that the difference is greater than the first threshold value, a second read operation is performed using a second voltage level that is distinct from the first voltage level.Type: GrantFiled: March 8, 2016Date of Patent: May 15, 2018Assignee: Macronix International Co., Ltd.Inventors: Chun Hsiung Hung, Han Sung Chen, Ming Chao Lin
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Publication number: 20180123592Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: CHUNG-KUANG CHEN, CHUN-HSIUNG HUNG, Han-Sung Chen
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Patent number: 9933977Abstract: A memory device includes a memory unit including a plurality of memory cells, and a controller including a storage unit that stores a plurality of operation selections each corresponding to a property of at least one selected memory cell among the plurality of memory cells.Type: GrantFiled: November 9, 2016Date of Patent: April 3, 2018Assignee: Macronix International Co., Ltd.Inventors: Chun-Hsiung Hung, Han-Sung Chen, Chung-Kuang Chen
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Patent number: 9887009Abstract: One aspect of the technology is a memory device, which comprises a plurality of page buffers and control circuitry. Different page buffer circuits in the plurality of page buffer circuits are coupled to different bit lines in a plurality of bit lines in a memory array. The control circuitry is responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells.Type: GrantFiled: October 14, 2014Date of Patent: February 6, 2018Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chung-Kuang Chen, Han-Sung Chen, Chung-Hsiung Hung
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Patent number: 9876502Abstract: The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.Type: GrantFiled: February 18, 2016Date of Patent: January 23, 2018Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chung-Kuang Chen, Chun-Hsiung Hung, Han-Sung Chen
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Publication number: 20170263310Abstract: A first read operation is performed using a first voltage level to read data from a memory array. An instant bit count corresponding to a number of bits in the data read from the memory array is determined. A recorded bit count corresponding to a number of bits in the data that was written at a time of writing the data to the memory array is accessed. A difference between the instant bit count and the recorded bit count is obtained. Conditioned on determining that the difference is less than or equal to a first threshold value, the data read from the memory array is output using the first read operation. Conditioned on determining that the difference is greater than the first threshold value, a second read operation is performed using a second voltage level that is distinct from the first voltage level.Type: ApplicationFiled: March 8, 2016Publication date: September 14, 2017Applicant: Macronix International Co., Ltd.Inventors: Chun Hsiung Hung, Han Sung Chen, Ming Chao Lin
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Patent number: 9679653Abstract: A method for programming a memory including a plurality of memory cells is provided. The method comprises selecting a cell and executing a program and program verify operation for the cell, including applying a sequence of program pulses and performing program verify steps. The sequence includes a starting pulse having a starting magnitude. The program verify steps use a program verify level. The method also comprises determining the starting magnitude for a next cell as a function of a magnitude of the program pulse in an instance of the program verify step in which the current cell passes verify at the program verify level.Type: GrantFiled: September 22, 2015Date of Patent: June 13, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ming-Chao Lin, Han-Sung Chen
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Patent number: 9589646Abstract: A page buffer circuit includes a plurality of page buffers including a first page buffer. The first page buffer is configured to load input data of the first page buffer, and input data of at least one neighboring page buffer. The first page buffer is also configured to apply a bias corresponding to the input data of the first page buffer, and the input data of the at least one neighboring page buffer to a bit line.Type: GrantFiled: November 26, 2014Date of Patent: March 7, 2017Assignee: Macronix International Co., Ltd.Inventors: Chung-Kuang Chen, Han-Sung Chen, Chun-Hsiung Hung
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Patent number: 9570133Abstract: A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver.Type: GrantFiled: December 13, 2012Date of Patent: February 14, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Han-Sung Chen, Chun-Hsiung Hung, Chung-Kuang Chen