Patents by Inventor Han Wei

Han Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240114134
    Abstract: An encoder includes circuitry and a memory coupled to the circuitry. The circuitry, in operation, determines whether or not a ternary split process of splitting a block into three sub blocks in a first direction parallel to a first longer side of the block is allowed by comparing a size of a second shorter side of the block to a minimum threshold value. The circuitry, responsive to the ternary split process being allowed, writes, into a bitstream, a split direction parameter indicative of a splitting direction. The circuitry, in operation, splits the block into a plurality of sub blocks in a direction indicated by the split direction parameter; and encodes the plurality of sub blocks. The minimum threshold value corresponds to a minimum size supported in a transform process.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 4, 2024
    Inventors: Sughosh Pavan SHASHIDHAR, Hai Wei SUN, Chong Soon LIM, Ru Ling LIAO, Han Boon TEO, Jing Ya LI, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Tadamasa TOMA
  • Publication number: 20240114136
    Abstract: An image encoder/decoder includes circuitry and a memory coupled to the circuitry. When a geometry of a block of a picture satisfies a first condition, the circuitry splits the block of the picture into sub blocks having a first set of geometries. When the geometry of the block does not satisfy the first condition, the circuitry splits the block of the picture into sub blocks having a second set of geometries, the second set of geometries being different from the first set of geometries. The circuitry encodes/decodes the sub blocks of the block.
    Type: Application
    Filed: December 6, 2023
    Publication date: April 4, 2024
    Inventors: Chong Soon LIM, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Han Boon TEO, Ru Ling LIAO, Takahiro NISHI, Tadamasa TOMA
  • Publication number: 20240114169
    Abstract: An encoder determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The encoder determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Jing Ya LI, Che Wei KUO, Chong Soon LIM, Chu Tong WANG, Han Boon TEO, Hai Wei SUN, Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA, Yusuke KATO
  • Publication number: 20240114160
    Abstract: An image decoder includes circuitry and a memory, wherein the circuitry, in operation, calculates first values of a first partition in a current block, using a first motion vector for the first partition; calculates second values of a second partition in the current block, using a second motion vector for the second partition; calculates third values of a set of pixels between the first partition and the second partition, using the first motion vector; calculates fourth values of the set of pixels, using the second motion vector; and weights the third values and the fourth values. A number of pixels in a row in the set of pixels is two or more, and two or more weights applied to the third values increase along the row.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 4, 2024
    Inventors: Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA, Ryuichi KANOH, Chong Soon LIM, Ru Ling LIAO, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Han Boon TEO, Jing Ya LI
  • Publication number: 20240111588
    Abstract: Intelligent process management is provided. A start time is determined for an additional process to be run on a worker node within a duration of a sleep state of a task of a process already running on the worker node by adding a first defined buffer time to a determined start time of the sleep state of the task. A backfill time is determined for the additional process by subtracting a second defined buffer time from a determined end time of the sleep state of the task. A scheduling plan is generated for the additional process based on the start time and the backfill time corresponding to the additional process. The scheduling plan is executed to run the additional process on the worker node according to the start time and the backfill time corresponding to the additional process.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Jing Jing Wei, Yue Wang, Shu Jun Tang, Yang Kang, Yi Fan Wu, Qi Han Zheng, Jia Lin Wang
  • Publication number: 20240110030
    Abstract: A styrene-modified polyethylene-based expandable resin particle is provided, which comprise a polyethylene resin and a polystyrene resin, wherein a content of the polyethylene resin ranges from 5 wt % to 30 wt % and a content of the polystyrene resin ranges from 70 wt % to 95 wt % based on 100 wt % of the polyethylene resin and the polystyrene resin, wherein the expandable resin particle comprises a xylene insoluble matter and an acetone insoluble matter, and a ratio of a content of the xylene insoluble matter to a content of the acetone insoluble matter ranges from 0.01 to 5. In addition, an expanded resin particle and a foamed resin molded article prepared by the aforesaid expandable resin particle are also provided. Furthermore, a method for manufacturing the aforesaid expandable resin particle is also provided.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 4, 2024
    Inventors: Han-Liou YI, Yao-Hsien CHUNG, Cheng-Ting HSIEH, Yu-Pin LIN, Keng-Wei HSU
  • Publication number: 20240114129
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation: determines whether a size of a current block, which is a unit for which a vector candidate list including vector candidates is generated, is less than or equal to a threshold; when the size of the current block is less than or equal to the threshold, generates the vector candidate list by registering a history-based motion vector predictor (HMVP) vector candidate in the vector candidate list from an HMVP table without performing a first pruning process; when the size of the current block is greater than the threshold, generates the vector candidate list by performing the first pruning process and registering the HMVP vector candidate in the vector candidate list from the HMVP table; and encodes the current block using the vector candidate list.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 4, 2024
    Inventors: Jing Ya LI, Chong Soon Lim, Han Boon Teo, Che Wei Kuo, Hai Wei Sun, Chu Tong Wang, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Yusuke Kato
  • Patent number: 11949884
    Abstract: An encoder encodes a video, and includes: circuitry; and memory coupled to the circuitry. Using the memory, the circuitry: obtains at least two items of prediction information for a first partition included in the video; derives at least one template from neighboring samples which neighbor the first partition; calculates at least two costs, using the at least one template and the at least two items of prediction information; using the at least two costs, (i) determines at least one splitting direction for the first partition or (ii) assigns one of the at least two items of prediction information to a second partition split from the first partition according to the splitting direction, and another thereof to a third partition split from the first partition according to the splitting direction; and encodes the first partition according to the splitting direction and the at least two items of prediction information.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: April 2, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Ryuichi Kanoh, Chong Soon Lim, Ru Ling Liao, Hai Wei Sun, Sughosh Pavan Shashidhar, Han Boon Teo, Jing Ya Li
  • Publication number: 20240105930
    Abstract: A transition metal layered oxide is a P2 type transition metal layered oxide which is represented by following formula (1). Na0.67-2xM1xMgaCubMn1-a-bO2??(1) In the formula (1), M1 is selected from a group consisting of calcium (Ca), potassium (K), magnesium (Mg), and lithium (Li), 0.01?a+b?0.5, 0.01?a?0.5, 0.01?b?0.5, and 0?x?0.2. A positive electrode material of a sodium-ion battery includes the above transition metal layered oxide.
    Type: Application
    Filed: November 22, 2022
    Publication date: March 28, 2024
    Applicant: National Tsing Hua University
    Inventors: Jin-Wei Kang, Han-Yi Chen
  • Publication number: 20240101425
    Abstract: A preparation method of a lithium iron phosphate cathode material includes steps of (a) providing a phosphoric acid, an iron powder, a carbon source, wherein the phosphoric acid and the iron powder are reacted to produce a first product, and the first product is amorphous iron phosphate with chemical formula of a-FePO4·xH2O (x>0); (b) providing a lithium salt mixture, wherein the lithium salt mixture includes a lithium hydroxide and a lithium carbonate; (c) grinding and mixing the first product, the carbon source, and the lithium salt mixture; (d) calcining the first product and the lithium salt mixture to produce a precursor, wherein the precursor has a formula of Fe3(PO4)2·8H2O+Li3PO4; and (e) calcining the precursor and the carbon source to obtain the lithium iron phosphate cathode material.
    Type: Application
    Filed: May 11, 2023
    Publication date: March 28, 2024
    Inventors: Han-Wei Hsieh, Yuan-Kai Lin
  • Publication number: 20240100517
    Abstract: The present disclosure provide a detection device of microfluidic polymerase chain reaction (PCR) and a detection system including the same. This all-in-one device and system may be used to detect at least one biological detection chip, so that can amplify gene fragments at the front-end and detect them at the back-end immediately, decreasing the time required for the analysis, enabling real-time, low-cost, and rapid detection of various viruses, such as EBV and COVID-19, without compromising accuracy or sensitivity.
    Type: Application
    Filed: September 27, 2022
    Publication date: March 28, 2024
    Inventors: HORN-JIUNN SHEEN, PEI-KUEN WEI, YU-JUI FAN, PO-HAN JUAN, YUNG-YU HUANG
  • Publication number: 20240105518
    Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Publication number: 20240097011
    Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: March 21, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
  • Publication number: 20240089479
    Abstract: An image encoder writes a first parameter and a second parameter to a bitstream, and derives a partition mode based on the first and second parameters. Responsive to the derived partition mode being a first partition mode, the image encoder executes the first partition mode including: splitting a block of a picture into a plurality of first blocks including a N×2N block sized N pixels by 2N pixels; splitting the N×2N block, wherein a ternary split is allowed to split the N×2N block in a vertical direction, which is a direction along the 2N pixels, into a plurality of sub blocks including at least one sub block sized N/4×2N, while a binary split is not allowed to split the N×2N block in the vertical direction into two sub blocks that are equally sized N/2×2N; and encoding the plurality of sub blocks.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Inventors: Chong Soon LIM, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Ru Ling LIAO, Han Boon TEO, Takahiro NISHI, Ryuichi KANOH, Tadamasa TOMA
  • Publication number: 20240089493
    Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: corrects a base motion vector using a correction value for correcting the base motion vector in a predetermined direction; and encodes a current partition to be encoded in an image of a video, using the base motion vector corrected. The correction value is specified by a first parameter and a second parameter, the first parameter indicating a table to be selected from among a plurality of tables each including values, the second parameter indicating one of the values included in the table to be selected indicated by the first parameter. In each of the plurality of tables, a smaller value among the values is assigned a smaller index. Each of the plurality of tables includes a different minimum value among the values.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Jing Ya LI, Chong Soon LIM, Ru Ling LIAO, Hai Wei SUN, Han Boon TEO, Kiyofumi ABE, Tadamasa TOMA, Takahiro NISHI
  • Publication number: 20240087877
    Abstract: A backside metallized compound semiconductor device includes a compound semiconductor wafer and a metal layered structure. The compound semiconductor wafer includes a substrate having opposite front and back surfaces, and a ground pad structure formed on the front surface. The substrate is formed with a via extending from the back surface to the front surface to expose a side wall of the substrate and a portion of the ground pad structure. The metal layered structure is disposed on the back surface, and covers the side wall and the portion of the ground pad structure. The metal layered structure includes an adhesion layer, a seed layer, a gold layer, and an electroplated copper layer that are formed on the back surface in such order. The method for manufacturing the backside metallized compound semiconductor device is also disclosed.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Tsung-Te CHIU, Kechuang LIN, Houng-Chi WEI, Chia-Chu KUO, Bing-Han CHUANG
  • Publication number: 20240088042
    Abstract: A semiconductor structure includes a dielectric layer over a substrate, a via conductor over the substrate and in the dielectric layer, and a first graphene layer disposed over the via conductor. In some embodiments, a top surface of the via conductor and a top surface of the dielectric layer are level. In some embodiments, the first graphene layer overlaps the via conductor from a top view. In some embodiments, the semiconductor structure further includes a second graphene layer under the via conductor and a third graphene layer between the dielectric layer and the via conductor. In some embodiments, the second graphene layer is between the substrate and the via conductor.
    Type: Application
    Filed: January 11, 2023
    Publication date: March 14, 2024
    Inventors: SHU-WEI LI, HAN-TANG HUNG, YU-CHEN CHAN, CHIEN-HSIN HO, SHIN-YI YANG, MING-HAN LEE, SHAU-LIN SHUE
  • Publication number: 20240088466
    Abstract: A recycling and reworking method of a lithium iron phosphate cathode material is disclosed and includes steps of: (a) providing a lithium iron phosphate recycled material; (b) oxidizing the lithium iron phosphate recycled material in an atmosphere at an oxidation temperature ranged from 300° C. to 400° C. for 1 hour to 5 hours to form a raw material powder composed of LiFePO4, Fe7(PO4)6, Fe2O3 and a residual carbon ranged from 0.07 wt. % to 0.6 wt. %; (c) grinding the raw material powder; (d) adjusting the composition of the raw material powder to form a precursor, which has the molar ratio of Li:P=0.99˜1.05:1, and the molar ratio of Fe:P=0.98˜1.02:1, wherein a carbon source is added; and (e) heat-treating the precursor in an inert gas at a sintering temperature ranged from 500° C. to 800° C. for 8 hours to 12 hours to form a lithium iron phosphate regenerated material.
    Type: Application
    Filed: May 9, 2023
    Publication date: March 14, 2024
    Inventors: Han-Wei Hsieh, Yi-Ting Li
  • Publication number: 20240090215
    Abstract: The method of forming the semiconductor structure includes the following steps. First trenches and second trenches are respectively formed in a substrate of the logic region and the substrate of the array region. A dielectric liner is formed in the first trenches and second trenches. First coating blocks and second coating blocks are respectively formed in the first trenches and second trenches. A cap layer is formed on the first coating blocks and the second coating blocks. Oxide structures are formed on the cap layer. Part of the oxide structures and part of the cap layer is removed. A semiconductor layer is formed in the array region and disposed on the substrate and between the oxide structures.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Inventors: Yuan-Huang WEI, Chien-Hsien WU, Hsiu-Han LIAO
  • Patent number: 11930206
    Abstract: An encoder which includes circuitry and memory. Using the memory, the circuitry generates a list which includes candidates for a first motion vector for a first partition. The list has a maximum list size and an order of the candidates, and at least one of the maximum list size or the order of the candidates is dependent on at least one of a partition size or a partition shape of the first partition. The circuitry selects the first motion vector from the candidates included in the list; encodes an index indicating the first motion vector among the candidates in the list into the bitstream based on the maximum list size; and generates the predicted image for the first partition using the first motion vector.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: March 12, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Chong Soon Lim, Hai Wei Sun, Sughosh Pavan Shashidhar, Han Boon Teo, Ru Ling Liao, Jing Ya Li, Tadamasa Toma, Takahiro Nishi, Kiyofumi Abe, Ryuichi Kanoh