Patents by Inventor Han Wei

Han Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079561
    Abstract: A cathode material and a preparation thereof are disclosed. The cathode material includes a core and a coating layer coated on the core. The core is formed by a ternary material having a composition of Li[NixCoyMnz]O2, wherein x+y+z=1, 0.8<x<1, 0<y<0.2, and 0<z<0.2. The coating layer is formed by an iron-phosphate compound material and includes a plurality of first particles aggregated. With high nickel content in the core, the cathode material with high energy density and low cost is realized. Since the iron-phosphate compound material has high-rate capability, the coating layer formed thereby further improves the rate capability of the cathode material.
    Type: Application
    Filed: May 3, 2023
    Publication date: March 7, 2024
    Inventor: Han-Wei Hsieh
  • Publication number: 20240077479
    Abstract: A detection system and method for the migrating cell is provided. The system is configured to detect a migrating cell combined with an immunomagnetic bead. The system includes a platform, a microchannel, a magnetic field source, a coherent light source and an optical sensing module. The microchannel is configured to allow the migrating cell to flow in it along a flow direction. The magnetic field source is configured to provide magnetic force to the migrating cell combined with the immunomagnetic bead. The magnetic force includes at least one magnetic force component and the magnetic force component is opposite to the flow direction of the microchannel. The coherent light source is configured to provide the microchannel with the coherent light. The optical sensing module is configured to receive the interference light caused by the coherent light being reflected by the sample inside the microchannel.
    Type: Application
    Filed: August 10, 2023
    Publication date: March 7, 2024
    Applicant: DeepBrain Tech. Inc
    Inventors: Han-Lin Wang, Chia-Wei Chen, Yao-Wen Liang, Ting-Chun Lin, Yun-Ting Kuo, You-Yin Chen, Yu-Chun Lo, Ssu-Ju Li, Ching-Wen Chang, Yi-Chen Lin
  • Publication number: 20240077343
    Abstract: Multiphase flowmeter aperture antenna transmission and pressure retention are disclosed herein. An example apparatus includes at least one radiating element to transmit or receive an electromagnetic signal along a measurement plane orthogonal to a direction of flow of the fluid in the vessel; a pressure retaining member to prevent fluid from entering the aperture antenna assembly through a measurement window of the aperture antenna assembly, at least a portion of the pressure retaining member to separate the radiating element and the fluid; and a metal housing with or without slits, the pressure retaining member to be at least partially within the metal housing, the radiating element to be coupled to the metal housing.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Inventors: Yu Ke Lim, Shasha Wang, Linyuan Zhan, Muhammad Fuad Bin Mohamed Zain, Kenny Shin Han Wei, Guillaume Jolivet, Cheng-Gang Xie
  • Publication number: 20240079758
    Abstract: An electronic device includes a metal back cover, a metal frame, and a first, second, third, and fourth radiators. The metal frame includes a discrete part and two connection parts. The connection parts are located by two sides of the discrete part, separated from the discrete part, and connected to the metal back cover. A U-shaped slot is formed between the discrete part and the metal back cover and between the discrete part and the connection parts. The first radiator is separated from the discrete part and includes a feed end. The second, third, and fourth radiators are connected to the discrete part and the metal back cover. The third radiator is located between the first and second radiators. The first radiator is located between the third and fourth radiators. The discrete part and the first, second, third, and fourth radiators form an antenna module together.
    Type: Application
    Filed: August 2, 2023
    Publication date: March 7, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Chih-Wei Liao, Hau Yuen Tan, Shih-Keng Huang, Wen-Hgin Chuang, Lin-Hsu Chiang, Chang-Hua Wu, Han-Wei Wang, Chun-Jung Hu
  • Patent number: 11924456
    Abstract: An encoder includes circuitry and a memory coupled to the circuitry, wherein the circuitry, in operation, performs a partition process. The partition process includes calculating first values of a set of pixels between a first partition and a second partition in a current block, using a first motion vector for the first partition; calculating second values of the set of pixels, using a second motion vector for the second partition; and calculating third values of the set of pixels by weighting the first values and the second values. When a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: March 5, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Ryuichi Kanoh, Chong Soon Lim, Ru Ling Liao, Hai Wei Sun, Sughosh Pavan Shashidhar, Han Boon Teo, Jing Ya Li
  • Patent number: 11924423
    Abstract: Provided is an encoder which includes circuitry and memory. Using the memory, the circuitry splits an image block into a plurality of partitions, obtains a prediction image for a partition, and encodes the image block using the prediction image. When the partition is not a non-rectangular partition, the circuitry obtains (i) a first prediction image for the partition, (ii) a gradient image for the first prediction image, and (iii) a second prediction image as the prediction image using the first prediction image and the gradient image. When the partition is a non-rectangular partition, the circuitry obtains the first prediction image as the prediction image without using the gradient image.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: March 5, 2024
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Ryuichi Kanoh, Chong Soon Lim, Ru Ling Liao, Hai Wei Sun, Sughosh Pavan Shashidhar, Han Boon Teo, Jing Ya Li
  • Publication number: 20240065372
    Abstract: A triboelectric nanosensor includes an elastic body, a liquid metal and a wire. The elastic body includes an inner wall surrounding a chamber, and a plurality of biomimetic shark placoid scale-shaped microstructures adjacent to each other and disposed at at least one portion of the inner wall. The liquid metal is located within the chamber and surrounded by the elastic body. The wire is electrically connected to the liquid metal. The elastic body is pressed to be deformed and restores to change a contact state between the liquid metal and the biomimetic shark placoid scale-shaped microstructures, thereby allowing a plurality of electrons to flow into the liquid metal via the wire or to flow out from the liquid metal via the wire.
    Type: Application
    Filed: November 10, 2022
    Publication date: February 29, 2024
    Inventors: Zong-Hong Lin, Cheng Yeh, Po-Han Wei, Fu-Cheng Kao
  • Publication number: 20240071822
    Abstract: A method for manufacturing a semiconductor structure includes forming a first interconnect feature in a first dielectric feature, the first interconnect feature including a first conductive element exposed from the first dielectric feature; forming a first cap feature over the first conductive element, the first cap feature including a first cap element which includes a two-dimensional material; forming a second dielectric feature with a first opening that exposes the first cap element; forming a barrier layer over the second dielectric feature while exposing the first cap element from the barrier layer; removing a portion of the first cap element exposed from the barrier layer; and forming a second conductive element in the first opening.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Lung CHUNG, Shin-Yi YANG, Yu-Chen CHAN, Han-Tang HUNG, Shu-Wei LI, Ming-Han LEE
  • Patent number: 11917150
    Abstract: Provided is an encoder which includes circuitry and memory. Using the memory, the circuitry splits an image block into a plurality of partitions, obtains a prediction image for a partition, and encodes the image block using the prediction image. When the partition is not a non-rectangular partition, the circuitry obtains (i) a first prediction image for the partition, (ii) a gradient image for the first prediction image, and (iii) a second prediction image as the prediction image using the first prediction image and the gradient image. When the partition is a non-rectangular partition, the circuitry obtains the first prediction image as the prediction image without using the gradient image.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: February 27, 2024
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Ryuichi Kanoh, Chong Soon Lim, Ru Ling Liao, Hai Wei Sun, Sughosh Pavan Shashidhar, Han Boon Teo, Jing Ya Li
  • Patent number: 11917179
    Abstract: A decoder includes circuitry which, in operation, parses a first flag indicating whether a CCALF (cross component adaptive loop filtering) process is enabled for a first block located adjacent to a left side of a current block; parses a second flag indicating whether the CCALF process is enabled for a second block located adjacent to an upper side of the current block; determines a first index associated with a color component of the current block; and derives a second index indicating a context model, using the first flag, the second flag, and the first index. The circuitry, in operation, performs entropy decoding of a third flag indicating whether the CCALF process is enabled for the current block, using the context model indicated by the second index; and performs the CCALF process on the current block in response to the third flag indicating the CCALF process is enabled for the current block.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: February 27, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Che-Wei Kuo, Chong Soon Lim, Han Boon Teo, Jing Ya Li, Hai Wei Sun, Chu Tong Wang, Tadamasa Toma, Takahiro Nishi, Kiyofumi Abe, Yusuke Kato
  • Publication number: 20240063370
    Abstract: A dual-cation metal battery and a charging and discharging method thereof are disclosed to reduce the cost of materials, maintain the long-term service life and provide multiple varied applications. The dual-cation metal battery includes a positive electrode, a negative electrode, an electrolyte solution and a separator. The positive electrode includes a positive-electrode material selected from the group consisting of heterosite (FePO4), lithium iron phosphate (LiFePO4) and LixNa1-xFePO4, and 0<x<1. The negative electrode includes a metal mixture consisting of lithium metal and sodium metal, and the weight ratio of lithium metal to sodium metal is 1:3. The electrolyte solution is disposed between the positive electrode and the negative electrode. The separator is disposed in the electrolyte solution, and the positive electrode and the negative electrode are separated from each other by the separator.
    Type: Application
    Filed: May 2, 2023
    Publication date: February 22, 2024
    Inventors: Han-Wei Hsieh, Yi-Ting Li, An-Feng Huang
  • Publication number: 20240030073
    Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.
    Type: Application
    Filed: July 19, 2023
    Publication date: January 25, 2024
    Inventors: Wei-De HO, Pei-Sheng Tang, Han-Wei Wu, Yuan-Hsiang Lung, Hua-Tai Lin, Chen-Jung Wang
  • Publication number: 20240023339
    Abstract: A method of forming a memory structure includes the following steps. A CMOS circuitry is formed over a semiconductor substrate. A bit line array is formed to be electrically connected to the CMOS circuitry. A memory array is formed over the bit line array. The memory array is formed by forming a word line stack, and forming first and second sets of stacked memory cells. The word line stack is formed on the bit line array and has a first side surface and a second side surface. The first sets of stacked memory cells are formed along the first side surface. The second sets of stacked memory cells are formed along the second side surface, wherein the second sets of stacked memory cells are staggered from the first sets of stacked memory cells. A source line array is formed over the memory array and electrically connected to the CMOS circuitry.
    Type: Application
    Filed: August 2, 2023
    Publication date: January 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hsuan Chien, Meng-Han Lin, Han-Wei Wu, Feng-Cheng Yang
  • Publication number: 20240020437
    Abstract: A method of generating a computational model includes generating a set of benchmark parameters indicative of material properties of a reference material system through performance of at least one of a simulation of, or an experiment on, a subset of the reference material system, generating a plurality of DFTB parameters for the reference material system, performing an optimization routine to adjust each DFTB parameter of the plurality of DFTB parameters to improve accuracy relative to the set of benchmark parameters of the reference material system, and storing an optimized set of DFTB parameters corresponding to the material properties of the reference material system.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 18, 2024
    Inventors: Tillmann C. Kubis, Han-Wei Hsiao
  • Publication number: 20230402277
    Abstract: A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.
    Type: Application
    Filed: June 12, 2022
    Publication date: December 14, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chin-Ta CHEN, Han-Wei WU, Yuan-Hsiang LUNG, Hua-Tai LIN
  • Publication number: 20230402767
    Abstract: An electronic device, including a metal back cover, a ground radiator, a third radiator, and a metal frame including a first cutting opening, a second cutting opening, a first radiator located between the first cutting opening and the second cutting opening, and a second radiator located beside the second cutting opening and separated from the first radiator by the second cutting opening, is provided. An end of a first slot formed between the metal back cover and a first part of the first radiator is communicated with the first cutting opening, and a second slot formed between the metal back cover and a second part of the first radiator and between the metal back cover and the second radiator is communicated with the second cutting opening. The ground radiator connects the metal back cover and the first radiator and separates the first slot from the second slot.
    Type: Application
    Filed: February 23, 2023
    Publication date: December 14, 2023
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Hau Yuen Tan, Chih-Wei Liao, Shih-Keng Huang, Wen-Hgin Chuang, Chia-Hong Chen, Lin-Hsu Chiang, Han-Wei Wang, Chun-Jung Hu
  • Patent number: 11844224
    Abstract: A method of forming a memory structure includes the following steps. A CMOS circuitry is formed over a semiconductor substrate. A bit line array is formed to be electrically connected to the CMOS circuitry. A memory array is formed over the bit line array. The memory array is formed by forming a word line stack, and forming first and second sets of stacked memory cells. The word line stack is formed on the bit line array and has a first side surface and a second side surface. The first sets of stacked memory cells are formed along the first side surface. The second sets of stacked memory cells are formed along the second side surface, wherein the second sets of stacked memory cells are staggered from the first sets of stacked memory cells. A source line array is formed over the memory array and electrically connected to the CMOS circuitry.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hsuan Chien, Meng-Han Lin, Han-Wei Wu, Feng-Cheng Yang
  • Patent number: 11837713
    Abstract: A preparation method of a cathode material for a secondary battery is provided. First, a lithium metal phosphate material and a first conductive carbon are provided. The lithium metal phosphate material is made of a plurality of secondary particles. Each of the secondary particles is formed by the aggregation of a plurality of primary particles. An interparticle space is formed between the plurality of primary particles. Next, the lithium metal phosphate material and the first conductive carbon are mixed by a mechanical method, and a composite material is prepared. The first conductive carbon is uniformly arranged in the interparticle space. After that, a second conductive carbon, a binder and a solvent are provided. Finally, the composite material, the second conductive carbon, the binder and the solvent are mixed, and a cathode material for preparing a positive plate is prepared.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 5, 2023
    Assignee: ADVANCED LITHIUM ELECTROCHEMISTRY CO., LTD.
    Inventors: Chen-Yi Huang, Han-Wei Hsieh, Yuan-Kai Lin, Chueh-Han Wang
  • Patent number: 11835371
    Abstract: Multiphase flowmeter aperture antenna transmission and pressure retention are disclosed herein. An example apparatus includes at least one radiating element to transmit or receive an electromagnetic signal along a measurement plane orthogonal to a direction of flow of the fluid in the vessel; a pressure retaining member to prevent fluid from entering the aperture antenna assembly through a measurement window of the aperture antenna assembly, at least a portion of the pressure retaining member to separate the radiating element and the fluid; and a metal housing with or without slits, the pressure retaining member to be at least partially within the metal housing, the radiating element to be coupled to the metal housing.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 5, 2023
    Assignee: Schlumberger Technology Corporation
    Inventors: Yu Ke Lim, Shasha Wang, Linyuan Zhan, Muhammad Fuad Bin Mohamed Zain, Kenny Shin Han Wei, Guillaume Jolivet, Cheng-Gang Xie
  • Patent number: D1015170
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: February 20, 2024
    Assignee: Garmin International, Inc.
    Inventors: Han-Wei Huang, Sean K. Stumpf, Todd P. Register, Jin-Ming Chen, Hsin Wei Tsai