Patents by Inventor Han-Wen LIAO
Han-Wen LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12249520Abstract: A wet etch apparatus includes a wafer chuck, a dispensing nozzle, a liquid etchant container, and an electric field generator. The dispensing nozzle is above the wafer chuck. The liquid etchant container is in fluid communication with the dispensing nozzle. The electric field generator is operative to generate an electric field across the wafer chuck. The electric field generator includes a first electrode and a second electrode spaced apart from the first electrode in a direction substantially perpendicular to a top surface of the wafer chuck, and the second electrode is an electrode plate above the wafer chuck.Type: GrantFiled: August 28, 2021Date of Patent: March 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hong-Ting Lu, Han-Wen Liao
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Publication number: 20240395572Abstract: A wet etch apparatus includes a wafer chuck, a dispensing nozzle above the wafer chuck, a rail, first and second vehicles, and an electric field generator. The rail extends at least from a first position aligned laterally with the wafer chuck to a second position higher than a top surface of the wafer chuck. The first and second vehicles are movable along the rail. The electric field generator is operative to generate an electric field across the wafer chuck. The electric field generator comprises a first electrode carried by the first vehicle and a second electrode carried by the second vehicle.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hong-Ting LU, Han-Wen LIAO
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Patent number: 12142664Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.Type: GrantFiled: May 18, 2021Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih Wei Bih, Han-Wen Liao, Xuan-You Yan, Yen-Yu Chen, Chun-Chih Lin
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Patent number: 11626315Abstract: A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.Type: GrantFiled: February 22, 2017Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Jung Huang, Hsu-Shui Liu, Han-Wen Liao, Yu-Yao Huang, Hsiao-Wei Chen, Yung-Lin Hsu, Kuang-Huan Hsu
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Patent number: 11367591Abstract: A plasma-processing apparatus includes a chamber, a plasma generator, and a composite plasma modulator. The chamber includes a plasma zone. The plasma generator is configured to generate a plasma in the plasma zone. The composite plasma modulator is configured to modulate the plasma. The composite plasma modulator includes a dielectric plate made of a first dielectric material and a first modulating portion made of a second dielectric material and coupled to the dielectric plate.Type: GrantFiled: January 30, 2017Date of Patent: June 21, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Han-Wen Liao
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Patent number: 11222788Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.Type: GrantFiled: August 21, 2020Date of Patent: January 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Wen Liao, Jun-Xiu Liu, Chun-Chih Lin
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Publication number: 20210391189Abstract: A wet etch apparatus includes a wafer chuck, a dispensing nozzle, a liquid etchant container, and an electric field generator. The dispensing nozzle is above the wafer chuck. The liquid etchant container is in fluid communication with the dispensing nozzle. The electric field generator is operative to generate an electric field across the wafer chuck. The electric field generator includes a first electrode and a second electrode spaced apart from the first electrode in a direction substantially perpendicular to a top surface of the wafer chuck, and the second electrode is an electrode plate above the wafer chuck.Type: ApplicationFiled: August 28, 2021Publication date: December 16, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hong-Ting LU, Han-Wen LIAO
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Publication number: 20210280692Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.Type: ApplicationFiled: May 18, 2021Publication date: September 9, 2021Inventors: Shih Wei Bih, Han-Wen Liao, Xuan-You Yan, Yen-Yu Chen, Chun-Chih Lin
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Patent number: 11107707Abstract: A method includes dispensing a chemical solution including charged ions onto a semiconductor substrate to chemically etch a target structure on the semiconductor substrate, and applying an electric field on the semiconductor substrate during dispensing the chemical solution on the semiconductor substrate, such that the charged ions in the chemical solution are moved in response to the electric field.Type: GrantFiled: June 11, 2019Date of Patent: August 31, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hong-Ting Lu, Han-Wen Liao
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Patent number: 11011426Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor fin over a substrate. A fin spacer is formed on a sidewall of the semiconductor fin. An e-beam treatment is performed on the fin spacer. An epitaxial structure is formed over the semiconductor fin. The epitaxial structure is in contact with the e-beam treated fin spacer.Type: GrantFiled: May 30, 2019Date of Patent: May 18, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Han-Wen Liao
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Patent number: 10879052Abstract: A method for manufacturing a semiconductor structure includes depositing a wafer in a processing chamber. Plasma is formed in the processing chamber to process the wafer. A plasma concentration over a peripheral region of the wafer is detected. A plasma distribution over the peripheral region of the wafer is adjusted according to the detected plasma concentration.Type: GrantFiled: July 24, 2019Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Han-Wen Liao
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Patent number: 10872760Abstract: A cluster tool includes a polyhedral transfer chamber, at least one processing chamber, at least one load lock chamber, and an electron beam (e-beam) source. The processing chamber is connected to the polyhedral transfer chamber. The processing chamber is configured to perform a manufacturing procedure to a wafer present therein. The load lock chamber is connected to the polyhedral transfer chamber. The e-beam source is configured to performing an e-beam treatment to the wafer after the wafer is performed the manufacturing procedure.Type: GrantFiled: July 26, 2016Date of Patent: December 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Han-Wen Liao
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Patent number: 10872788Abstract: A method includes dispensing a liquid etchant onto a wafer, wherein the wafer is free from rotation during dispensing the liquid etchant; blowing the liquid etchant on the wafer using a gas flow, wherein a direction of the gas flow remains substantially constant during dispensing the liquid etchant; and turning the gas flow off after a target structure on the wafer is etched away by the liquid etchant.Type: GrantFiled: August 15, 2019Date of Patent: December 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hong-Ting Lu, Han-Wen Liao
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Publication number: 20200395220Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.Type: ApplicationFiled: August 21, 2020Publication date: December 17, 2020Inventors: Han-Wen LIAO, Jun-Xiu LIU, Chun-Chih LIN
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Patent number: 10784114Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.Type: GrantFiled: October 31, 2019Date of Patent: September 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Wen Liao, Jun-Xiu Liu, Chun-Chih Lin
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Publication number: 20200168479Abstract: A method includes dispensing a chemical solution including charged ions onto a semiconductor substrate to chemically etch a target structure on the semiconductor substrate, and applying an electric field on the semiconductor substrate during dispensing the chemical solution on the semiconductor substrate, such that the charged ions in the chemical solution are moved in response to the electric field.Type: ApplicationFiled: June 11, 2019Publication date: May 28, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hong-Ting LU, Han-Wen LIAO
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Publication number: 20200168480Abstract: A method includes dispensing a liquid etchant onto a wafer, wherein the wafer is free from rotation during dispensing the liquid etchant; blowing the liquid etchant on the wafer using a gas flow, wherein a direction of the gas flow remains substantially constant during dispensing the liquid etchant; and turning the gas flow off after a target structure on the wafer is etched away by the liquid etchant.Type: ApplicationFiled: August 15, 2019Publication date: May 28, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hong-Ting LU, Han-Wen LIAO
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Publication number: 20200161102Abstract: A method for manufacturing a semiconductor structure includes depositing a wafer in a processing chamber. Plasma is formed in the processing chamber to process the wafer. A plasma concentration over a peripheral region of the wafer is detected. A plasma distribution over the peripheral region of the wafer is adjusted according to the detected plasma concentration.Type: ApplicationFiled: July 24, 2019Publication date: May 21, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Han-Wen LIAO
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Publication number: 20200161188Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor fin over a substrate. A fin spacer is formed on a sidewall of the semiconductor fin. An e-beam treatment is performed on the fin spacer. An epitaxial structure is formed over the semiconductor fin. The epitaxial structure is in contact with the e-beam treated fin spacer.Type: ApplicationFiled: May 30, 2019Publication date: May 21, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Han-Wen LIAO
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Publication number: 20200066538Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.Type: ApplicationFiled: October 31, 2019Publication date: February 27, 2020Inventors: Han-Wen LIAO, Jun Xiu LIU, Chun-Chih LIN