Patents by Inventor Han-Wen LIAO

Han-Wen LIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10504737
    Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Wen Liao, Jun Xiu Liu, Chun-Chih Lin
  • Patent number: 10446662
    Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: October 15, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Wei Bih, Han-Wen Liao, Xuan-You Yan, Yen-Yu Chen, Chun-Chih Lin
  • Publication number: 20180350948
    Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 6, 2018
    Inventors: Shih Wei Bih, Han-Wen Liao, Xuan-You Yan, Yen-Yu Chen, Chun-Chih Lin
  • Publication number: 20180350614
    Abstract: Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 6, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Wen Liao, Jun Xiu Liu, Chun-Chih Lin
  • Patent number: 10026638
    Abstract: A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process chamber. The wafer stage is configured to secure a process wafer. The system further includes a bottom electrode positioned beneath the wafer stage, a top electrode positioned external to the chamber, and a plasma distribution mechanism. The plasma distribution mechanism is reconfigurable to allow for more than one plasma distribution profile.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: July 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Han-Wen Liao
  • Publication number: 20180174883
    Abstract: A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process chamber. The wafer stage is configured to secure a process wafer. The system further includes a bottom electrode positioned beneath the wafer stage, a top electrode positioned external to the chamber, and a plasma distribution mechanism. The plasma distribution mechanism is reconfigurable to allow for more than one plasma distribution profile.
    Type: Application
    Filed: December 15, 2016
    Publication date: June 21, 2018
    Inventor: Han-Wen Liao
  • Publication number: 20180158653
    Abstract: A plasma-processing apparatus includes a chamber, a plasma generator, and a composite plasma modulator. The chamber includes a plasma zone. The plasma generator is configured to generate a plasma in the plasma zone. The composite plasma modulator is configured to modulate the plasma. The composite plasma modulator includes a dielectric plate made of a first dielectric material and a first modulating portion made of a second dielectric material and coupled to the dielectric plate.
    Type: Application
    Filed: January 30, 2017
    Publication date: June 7, 2018
    Inventor: Han-Wen Liao
  • Publication number: 20180151412
    Abstract: A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.
    Type: Application
    Filed: February 22, 2017
    Publication date: May 31, 2018
    Inventors: Chun-Jung Huang, Hsu-Shui Liu, Han-Wen Liao, Yu-Yao Huang, Hsiao-Wei Chen, Yung-Lin Hsu, Kuang-Huan Hsu
  • Publication number: 20180102418
    Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.
    Type: Application
    Filed: January 31, 2017
    Publication date: April 12, 2018
    Inventors: Shih Wei Bih, Han-Wen Liao, Xuan-You Yan, Yen-Yu Chen, Chun-Chih Lin
  • Publication number: 20180033611
    Abstract: A cluster tool includes a polyhedral transfer chamber, at least one processing chamber, at least one load lock chamber, and an electron beam (e-beam) source. The processing chamber is connected to the polyhedral transfer chamber. The processing chamber is configured to perform a manufacturing procedure to a wafer present therein. The load lock chamber is connected to the polyhedral transfer chamber. The e-beam source is configured to performing an e-beam treatment to the wafer after the wafer is performed the manufacturing procedure.
    Type: Application
    Filed: July 26, 2016
    Publication date: February 1, 2018
    Inventor: Han-Wen Liao
  • Patent number: 9412606
    Abstract: One or more systems and methods for controlling a target dimension for a wafer are provided. A processing chamber, such as an etching chamber, is configured to etch one or more wafers. In some embodiments, during processing of a first wafer of a set of wafers, the processing chamber is coated with a relatively thicker chamber coating than chamber coatings used for subsequently processed wafers of the set of wafers. The increased chamber coating thickness results in the first wafer having a target dimension that is substantially similar to target dimensions of the subsequently processed wafers. In some embodiments, a post wafer cleaning process is performed, but a pre wafer cleaning process is disabled, between processing a final wafer of a first set of wafers and an initial wafer of a second set of wafers so that the final wafer and the initial wafer have substantially similar target dimensions.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
  • Patent number: 9362185
    Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsi Wu, Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
  • Patent number: 9324578
    Abstract: One or more systems and methods for reshaping a hard mask are provided. A semiconductor arrangement comprises one or more structures formed from a layer according to a target dimension, such as a width criterion, a length criterion, a spacing criterion, or other design constraints. To form such a structure, a hard mask is formed over the layer. Responsive to a dimension, such as a width, of the hard mask not corresponding to the target dimension, a first hard mask portion is modified to create a modified hard mask comprising a modified first hard mask portion. In some embodiments, the first hard mask portion is trimmed to decrease the dimension or coated with a coating material to increase the dimension. An etch of the layer is performed through the modified hard mask to create an etched layer comprising an etched portion, such as the structure, corresponding to the target dimension.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: April 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
  • Publication number: 20150279750
    Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.
    Type: Application
    Filed: June 10, 2015
    Publication date: October 1, 2015
    Inventors: Chung-Hsi Wu, Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
  • Publication number: 20150235877
    Abstract: One or more systems and methods for controlling a target dimension for a wafer are provided. A processing chamber, such as an etching chamber, is configured to etch one or more wafers. In some embodiments, during processing of a first wafer of a set of wafers, the processing chamber is coated with a relatively thicker chamber coating than chamber coatings used for subsequently processed wafers of the set of wafers. The increased chamber coating thickness results in the first wafer having a target dimension that is substantially similar to target dimensions of the subsequently processed wafers. In some embodiments, a post wafer cleaning process is performed, but a pre wafer cleaning process is disabled, between processing a final wafer of a first set of wafers and an initial wafer of a second set of wafers so that the final wafer and the initial wafer have substantially similar target dimensions.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Inventors: Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
  • Publication number: 20150214063
    Abstract: One or more systems and methods for reshaping a hard mask are provided. A semiconductor arrangement comprises one or more structures formed from a layer according to a target dimension, such as a width criterion, a length criterion, a spacing criterion, or other design constraints. To form such a structure, a hard mask is formed over the layer. Responsive to a dimension, such as a width, of the hard mask not corresponding to the target dimension, a first hard mask portion is modified to create a modified hard mask comprising a modified first hard mask portion. In some embodiments, the first hard mask portion is trimmed to decrease the dimension or coated with a coating material to increase the dimension. An etch of the layer is performed through the modified hard mask to create an etched layer comprising an etched portion, such as the structure, corresponding to the target dimension.
    Type: Application
    Filed: January 29, 2014
    Publication date: July 30, 2015
    Inventors: Hans-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
  • Patent number: 9087793
    Abstract: A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: July 21, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Wen Liao, Wei-Tai Lin, Wen-Sheng Wang, Chih-Yu Lin, Cherng-Chang Tsuei, Chen-Hsiang Lu
  • Publication number: 20150179531
    Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Hsi Wu, Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
  • Patent number: 9064741
    Abstract: A method for patterning a wafer includes performing a first patterning on a wafer, and after performing the first patterning, calculating a simulated dose mapper (DoMa) map predicting a change in critical dimensions of the wafer due to performing a second patterning on the wafer. The method further includes performing the second patterning on the wafer. Performing the second patterning includes adjusting one or more etching parameters of the second patterning in accordance with differences between the simulated DoMa map and desired critical dimensions of the wafer.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Hsi Wu, Han-Wen Liao, Chih-Yu Lin, Cherng-Chang Tsuei
  • Publication number: 20150162206
    Abstract: A method for etching a target layer of a semiconductor device in an etching apparatus is provided. To form an element, the method includes forming a photoresist pattern on the target layer of the semiconductor device, in which the photoresist pattern has an after-develop-inspection critical dimension (ADI CD). A target after-etch-inspection critical dimension (AEI CD) of the element is provided, as well as a trim time of the target layer. The etching apparatus is provided and a formation time of a protective layer on an inner wall of the etching apparatus is determined based on the ADI CD, the target AEI CD and the trim time. The protective layer for the predetermined formation time is formed to perform a trimming process on the target layer for the trim time by using the photoresist pattern as a mask, so as to form the element.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 11, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Wen LIAO, Wei-Tai LIN, Wen-Sheng WANG, Chih-Yu LIN, Cherng-Chang TSUEI, Chen-Hsiang LU