Patents by Inventor Han YEH

Han YEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210217691
    Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.
    Type: Application
    Filed: March 31, 2021
    Publication date: July 15, 2021
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Chiung-Han Yeh
  • Publication number: 20210209779
    Abstract: A method for detecting dimension of box based on depth map includes: receiving a depth map generated by a camera, the depth map corresponds to pixels of an image including a box; performing a coordinate transformation to transform the depth map into camera coordinates of each of the pixels; dividing some of the pixels into plural blocks, each of blocks includes a number of the pixels adjacent to each other; statistically analyzing an average normal vector of each of the blocks according to the camera coordinates of the pixels of each of the blocks; classifying the blocks into plural clusters according to the average normal vector of each of the blocks; performing a plane extraction to obtain edge vectors according to plane formulas of the clusters; obtaining vertexes of the box according to the edge vectors; and obtaining a dimension of the box according the vertexes.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 8, 2021
    Inventor: Ying-Han YEH
  • Patent number: 11037861
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • Patent number: 11018241
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu, Bao-Ru Young
  • Patent number: 10971441
    Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Chiung-Han Yeh
  • Patent number: 10943530
    Abstract: A mura compensation apparatus for an organic light emitting diode (OLED) display includes a calculator and a mura compensator. The calculator is configured to calculate a non-maximum-luminance demura offset value of a pixel of the OLED display for a determined gray level on the basis of a gamma value, a maximum-luminance demura offset value of the pixel of the OLED display for a relocated gray level and a non-maximum luminance value of the OLED display. The mura compensator is configured to perform mura compensation on the pixel of the OLED display by the non-maximum-luminance demura offset value for the determined gray level.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: March 9, 2021
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventor: Ying-Han Yeh
  • Patent number: 10943548
    Abstract: A image adjustment method applicable to a display includes: defining multiple areas on a display region of the display; obtaining statistics of grayscale of a preliminary image; determining an image type of the preliminary image according to the statistics of grayscale of the preliminary image; generating a Cumulative Distribution Function (CDF) of luminance according to the statistics of grayscale of the preliminary image; individually adjusting a backlight level for each of the areas according to the CDF and the image type of the preliminary image; and generating an output image with each of the areas being individually adjusted.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 9, 2021
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Bo-Ruei Lin, Ying-Han Yeh
  • Publication number: 20210065637
    Abstract: A image adjustment method applicable to a display includes: defining multiple areas on a display region of the display; obtaining statistics of grayscale of a preliminary image; determining an image type of the preliminary image according to the statistics of grayscale of the preliminary image; generating a Cumulative Distribution Function (CDF) of luminance according to the statistics of grayscale of the preliminary image; individually adjusting a backlight level for each of the areas according to the CDF and the image type of the preliminary image; and generating an output image with each of the areas being individually adjusted.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 4, 2021
    Inventors: Bo-Ruei Lin, Ying-Han Yeh
  • Patent number: 10882296
    Abstract: A film-peeling apparatus is adapted to peel a protective film on a surface of a substrate. The surface of the substrate has a bare area which is not covered by the protective film. The film-peeling apparatus includes a punching member, a connector connected to the punching member, and a controller. The controller is configured for driving, through the connector, the punching member to punch at predetermined positions nearby or on a first edge of the protective film adjacent to the bare area.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: January 5, 2021
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Shang-Chi Wang, Yun-Han Yeh, Cyuan-Bang Wu
  • Publication number: 20200279935
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu, Bao-Ru Young
  • Patent number: 10726247
    Abstract: A system and method for monitoring qualities of teaching and learning are provided. The system includes at least one receiving interface, a processor, and an output apparatus, wherein the processor is electrically connected to the at least one receiving interface and the output apparatus. The at least one receiving interface receives at least one digital image. The processor identifies at least one facial message from the at least one digital image, identifies at least one body message from the at least one digital image, and determines at least one teaching and learning quality index according to the at least one facial message and the at least one body message. The output apparatus outputs the at least one facial message, the at least one body message, and the at least one teaching and learning quality index.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 28, 2020
    Assignee: Institute For Information Industry
    Inventors: I-Chang Tsai, Chao-Hung Liao, Chung-Han Yeh, Han-Yen Yu, Yu-Te Ku
  • Publication number: 20200232119
    Abstract: A method of forming a single-crystal group-III nitride is provided in the present invention. In some embodiments, the method includes the following steps. First, a molybdenum disulfide (MoS2) is formed on a remote substrate. Then, the MoS2 is transferred onto a substrate. Next, a sputtering operation is performed to epitaxially grow a single-crystal group-III nitride layer on the MoS2, so as to form the single-crystal group-III nitride layer on the substrate such as a Si substrate or a flexible substrate.
    Type: Application
    Filed: July 24, 2019
    Publication date: July 23, 2020
    Inventors: Jie-He CHEN, Yu-Kai HSU, Xiang-Zhu XIE, Min-Jie LIOU, Hui-Ling KAO, Wen-Hao CHANG, Jyh-Shin CHEN, Po-Chun KUO, Li-Syuan LU, Han YEH
  • Patent number: 10658492
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu, Bao-Ru Young
  • Patent number: 10600370
    Abstract: A local dimming system includes a mean estimation unit that estimates a mean value of an image; a PWM gain control unit that generates a PWM gain value according to the mean value; a spatial filter that performs on a plurality of the mean values in spatial domain to enhance a plurality of the PWM gain values, thereby generating enhanced PWM gain values; a scene change detection unit that detects scene change according to a histogram mean value generated by the mean estimation unit; a temporal filter that performs in temporal domain according to the enhanced PWM gain values and a result of scene change detection, thereby generating PWM values; a light shape imitation (LSI) unit that generates luminance gain according to the PWM value; and a pixel compensation unit that performs pixel compensation on the image according to the luminance gain, thereby resulting in a compensated image.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 24, 2020
    Assignee: Himax Technologies Limited
    Inventors: Yun-Sheng Lin, Li-Chia Chu, Ying-Han Yeh
  • Publication number: 20200083145
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • Publication number: 20200066214
    Abstract: A local dimming system includes a mean estimation unit that estimates a mean value of an image; a PWM gain control unit that generates a PWM gain value according to the mean value; a spatial filter that performs on a plurality of the mean values in spatial domain to enhance a plurality of the PWM gain values, thereby generating enhanced PWM gain values; a scene change detection unit that detects scene change according to a histogram mean value generated by the mean estimation unit; a temporal filter that performs in temporal domain according to the enhanced PWM gain values and a result of scene change detection, thereby generating PWM values; a light shape imitation (LSI) unit that generates luminance gain according to the PWM value; and a pixel compensation unit that performs pixel compensation on the image according to the luminance gain, thereby resulting in a compensated image.
    Type: Application
    Filed: August 22, 2018
    Publication date: February 27, 2020
    Inventors: Yun-Sheng Lin, Li-Chia Chu, Ying-Han Yeh
  • Publication number: 20200034607
    Abstract: A system and method for monitoring qualities of teaching and learning are provided. The system includes at least one receiving interface, a processor, and an output apparatus, wherein the processor is electrically connected to the at least one receiving interface and the output apparatus. The at least one receiving interface receives at least one digital image. The processor identifies at least one facial message from the at least one digital image, identifies at least one body message from the at least one digital image, and determines at least one teaching and learning quality index according to the at least one facial message and the at least one body message. The output apparatus outputs the at least one facial message, the at least one body message, and the at least one teaching and learning quality index.
    Type: Application
    Filed: August 31, 2018
    Publication date: January 30, 2020
    Inventors: I-Chang TSAI, Chao-Hung LIAO, Chung-Han YEH, Han-Yen YU, Yu-Te KU
  • Publication number: 20200020623
    Abstract: A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures.
    Type: Application
    Filed: September 22, 2019
    Publication date: January 16, 2020
    Inventors: Shuo-Mao Chen, Der-Chyang Yeh, Chiung-Han Yeh
  • Patent number: 10532551
    Abstract: A foil peeling apparatus adapted to a substrate having a foil thereon includes a foil peeling member, a connector and a controller. The foil peeling member has a foil peeling surface. The controller controls the connector to drive the peeling member to move along a path. The foil peeling surface of the peeling member in contact with, with an initial angle, the substrate, feeds toward the substrate for a first displacement, and then moves upwards and toward the substrate when the first feeding angle is decreased.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: January 14, 2020
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Shang-Chi Wang, Yun-Han Yeh, Cyuan-Bang Wu
  • Patent number: 10515875
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh