Patents by Inventor Han-Yu Lin

Han-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11830928
    Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Yu Lin, Chansyun David Yang, Tze-Chung Lin, Fang-Wei Lee, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11830948
    Abstract: A semiconductor device includes a semiconductor substrate, at least one semiconductor fin and a gate stack. The semiconductor fin is disposed on the semiconductor substrate. The semiconductor fin includes a first portion, a second portion and a first neck portion between the first portion and the second portion. A width of the first portion decreases as the first portion becomes closer to the first neck portion, and a width of the second portion increases as the second portion becomes closer to a bottom surface of the semiconductor substrate. The gate stack partially covers the semiconductor fin.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Ming Kuo, Hsin-Chih Chen, Che-Yuan Hsu, Kuo-Chin Liu, Han-Yu Tsai, You-Ting Lin, Jen-Hong Chang
  • Publication number: 20230324787
    Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.
    Type: Application
    Filed: June 15, 2023
    Publication date: October 12, 2023
    Inventors: Kuo-Hao LEE, You-Cheng JHANG, Han-Zong PAN, Jui-Chun WENG, Chiu-Hua CHUNG, Sheng-Yuan LIN, Hsin-Yu CHEN
  • Publication number: 20230317674
    Abstract: Semiconductor devices and methods are provided which facilitate improved thermal conductivity using a high-kappa dielectric bonding layer. In at least one example, a device is provided that includes a first substrate. A semiconductor device layer is disposed on the first substrate, and the semiconductor device layer includes one or more semiconductor devices. Frontside interconnect structure are disposed on the semiconductor device layer, and a bonding layer is disposed on the frontside interconnect structure. A second substrate is disposed on the bonding layer. The bonding layer has a thermal conductivity greater than 10 W/m·K.
    Type: Application
    Filed: January 6, 2023
    Publication date: October 5, 2023
    Inventors: Che Chi SHIH, Cheng-Ting CHUNG, Han-Yu LIN, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20230302638
    Abstract: A stabilization method incorporated with a mobile robot having a body, a plane-pressure sensor, and a movement mechanism is disclosed and includes the following steps: sensing and obtaining a pressure distribution of the body through the plane-pressure sensor; computing a center of gravity (CoG) position of the body in accordance with the pressure distribution; determining whether the CoG position is located within a steady zone pre-defined upon the body; and, providing a reverse force toward a CoG offset direction of the CoG position when the CoG position is determined to be off the steady zone.
    Type: Application
    Filed: August 4, 2022
    Publication date: September 28, 2023
    Inventors: Cheng-Hao HUANG, Po-Chiao HUANG, Han-Ching LIN, Shi-Yu WANG
  • Publication number: 20230282520
    Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.
    Type: Application
    Filed: May 8, 2023
    Publication date: September 7, 2023
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
  • Publication number: 20230268386
    Abstract: A device includes a first semiconductor structure, a second semiconductor structure, and an isolation structure which is disposed between the first and second semiconductor structures, and which includes a dielectric material having a dielectric constant higher than 8 and lower than 16. A method for manufacturing the device is also disclosed.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Yu LIN, Che-Chi SHIH, Szu-Hua CHEN, Kuan-Da HUANG, Cheng-Ming LIN, Tze-Chung LIN, Li-Te LIN, Wei-Yen WOON, Pinyen LIN
  • Patent number: 11726401
    Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Hao Lee, You-Cheng Jhang, Han-Zong Pan, Jui-Chun Weng, Chiu-Hua Chung, Sheng-Yuan Lin, Hsin-Yu Chen
  • Publication number: 20230215936
    Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Yu LIN, Chansyun David YANG, Fang-Wei LEE, Tze-Chung LIN, Li-Te LIN, Pinyen LIN
  • Publication number: 20230141093
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.
    Type: Application
    Filed: January 2, 2023
    Publication date: May 11, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu LIN, Jhih-Rong HUANG, Yen-Tien TUNG, Tzer-Min SHEN, Fu-Ting YEN, Gary CHAN, Keng-Chu LIN, Li-Te LIN, Pinyen LIN
  • Patent number: 11646234
    Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: May 9, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
  • Publication number: 20230118700
    Abstract: A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 20, 2023
    Inventors: Han-Yu Lin, Chansyun David Yang, Tze-Chung Lin, Fang-Wei Lee, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
  • Patent number: 11605728
    Abstract: A semiconductor device structure is provided. The semiconductor device includes a first nanowire structure over a second nanowire structure, a gate stack wrapping around the first nanowire structure and the second nanowire structure, a source/drain feature adjoining the first nanowire structure and the second nanowire structure, a gate spacer layer over the first nanowire structure and between the gate stack and the source/drain feature, and an inner spacer layer between the first nanowire structure and the second nanowire structure and between the gate stack and the source/drain feature. The gate spacer layer has a first carbon concentration, the inner spacer has a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: March 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Yu Lin, Chansyun David Yang, Fang-Wei Lee, Tze-Chung Lin, Li-Te Lin, Pinyen Lin
  • Publication number: 20230067696
    Abstract: A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Yi-Shan Chen, Kuan-Da Huang, Han-Yu Lin, Li-Te Lin, Ming-Huan Tsai
  • Publication number: 20230064393
    Abstract: The present disclosure describes a method that includes forming a fin structure with a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the second semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening and etching a portion of the second semiconductor layer with a fluorine-containing gas through the opening.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tze-Chung LIN, Han-Yu LIN, Fang-Wei LEE, Li-Te LIN, Pinyen LIN
  • Publication number: 20230020731
    Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.
    Type: Application
    Filed: November 23, 2021
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu Lin, Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon, Pinyen Lin, Che Chi Shih
  • Publication number: 20230017512
    Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tze-Chung LIN, Pinyen LIN, Fang-Wei LEE, Li-Te LIN, Han-yu LIN
  • Publication number: 20230009745
    Abstract: A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.
    Type: Application
    Filed: July 8, 2021
    Publication date: January 12, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ming LIN, Han-Yu LIN, Wei-Yen WOON, Mrunal Abhijith KHADERBAD
  • Patent number: 11545397
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: January 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Yu Lin, Jhih-Rong Huang, Yen-Tien Tung, Tzer-Min Shen, Fu-Ting Yen, Gary Chan, Keng-Chu Lin, Li-Te Lin, Pinyen Lin
  • Publication number: 20220336635
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first semiconductor layers and second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers, and removing a portion of the first semiconductor layers and second semiconductor layers to form a S/D trench. The method also includes removing the second semiconductor layers to form a recess connected to the S/D trench. The method includes forming a dummy dielectric layer in the recess after the dummy gate structure is formed, and the dummy dielectric layer is exposed by the S/D trench. The method includes removing a portion of the dummy dielectric layer to form a cavity and forming an inner spacer layer in the cavity.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tze-Chung LIN, Han-Yu LIN, Li-Te LIN, Pinyen LIN