Patents by Inventor Han-Yu Lin
Han-Yu Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11951637Abstract: A calibration apparatus includes a processor, an alignment device, and an arm. The alignment device captures images in a three-dimensional space, and a tool is arranged on a flange of the arm. The processor records a first matrix of transformation between an end-effector coordinate-system and a robot coordinate-system, and performs a tool calibration procedure according to the images captured by the alignment device for obtaining a second matrix of transformation between a tool coordinate-system and the end-effector coordinate-system. The processor calculates relative position of a tool center point of the tool in the robot coordinate-system based on the first and second matrixes, and controls the TCP to move in the three-dimensional space for performing a positioning procedure so as to regard points in an alignment device coordinate-system as points of the TCP, and calculates the relative positions of points in the alignment device coordinate-system and in the robot coordinate-system.Type: GrantFiled: June 4, 2021Date of Patent: April 9, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Cheng-Hao Huang, Shi-Yu Wang, Po-Chiao Huang, Han-Ching Lin, Meng-Zong Li
-
Publication number: 20240097011Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITEDInventors: Han-Yu LIN, Fang-Wei LEE, Kai-Tak LAM, Raghunath PUTIKAM, Tzer-Min SHEN, Li-Te LIN, Pinyen LIN, Cheng-Tzu YANG, Tzu-Li LEE, Tze-Chung LIN
-
Publication number: 20240086609Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.Type: ApplicationFiled: February 16, 2023Publication date: March 14, 2024Inventors: Cheng-YU LIN, Chia Chun WU, Han-Chung CHANG, Chih-Liang CHEN
-
Patent number: 11908685Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, where the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.Type: GrantFiled: March 15, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Ruei Jhan, Han-Yu Lin, Li-Te Lin, Pinyen Lin
-
Publication number: 20240030281Abstract: A semiconductor device having a low-k isolation structure and a method for forming the same are provided. The semiconductor device includes channel structures, laterally extending on a substrate; gate structures, intersecting and covering the channel structures; and a channel isolation structure, laterally penetrating through at least one of the channel structures, and extending between separate sections of one of the gate structures along an extending direction of the one of the gate structures. A low-k dielectric material in the channel isolation structure comprises boron nitride.Type: ApplicationFiled: July 21, 2022Publication date: January 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Hua Chen, Cheng-Ming Lin, Han-Yu Lin, Wei-Yen Woon, Ming-Jie Huang, Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Szuya Liao
-
Patent number: 11855192Abstract: A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.Type: GrantFiled: January 19, 2021Date of Patent: December 26, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITEDInventors: Han-Yu Lin, Fang-Wei Lee, Kai-Tak Lam, Raghunath Putikam, Tzer-Min Shen, Li-Te Lin, Pinyen Lin, Cheng-Tzu Yang, Tzu-Li Lee, Tze-Chung Lin
-
Patent number: 11830928Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.Type: GrantFiled: August 26, 2021Date of Patent: November 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Yu Lin, Chansyun David Yang, Tze-Chung Lin, Fang-Wei Lee, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
-
Publication number: 20230317674Abstract: Semiconductor devices and methods are provided which facilitate improved thermal conductivity using a high-kappa dielectric bonding layer. In at least one example, a device is provided that includes a first substrate. A semiconductor device layer is disposed on the first substrate, and the semiconductor device layer includes one or more semiconductor devices. Frontside interconnect structure are disposed on the semiconductor device layer, and a bonding layer is disposed on the frontside interconnect structure. A second substrate is disposed on the bonding layer. The bonding layer has a thermal conductivity greater than 10 W/m·K.Type: ApplicationFiled: January 6, 2023Publication date: October 5, 2023Inventors: Che Chi SHIH, Cheng-Ting CHUNG, Han-Yu LIN, Wei-Yen WOON, Szuya LIAO
-
Publication number: 20230282520Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.Type: ApplicationFiled: May 8, 2023Publication date: September 7, 2023Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
-
Publication number: 20230268386Abstract: A device includes a first semiconductor structure, a second semiconductor structure, and an isolation structure which is disposed between the first and second semiconductor structures, and which includes a dielectric material having a dielectric constant higher than 8 and lower than 16. A method for manufacturing the device is also disclosed.Type: ApplicationFiled: February 23, 2022Publication date: August 24, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Yu LIN, Che-Chi SHIH, Szu-Hua CHEN, Kuan-Da HUANG, Cheng-Ming LIN, Tze-Chung LIN, Li-Te LIN, Wei-Yen WOON, Pinyen LIN
-
Publication number: 20230215936Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.Type: ApplicationFiled: March 13, 2023Publication date: July 6, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Yu LIN, Chansyun David YANG, Fang-Wei LEE, Tze-Chung LIN, Li-Te LIN, Pinyen LIN
-
Publication number: 20230141093Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a sacrificial layer. The method can further include forming a first recess structure in a first portion of the fin structure, forming a second recess structure in the sacrificial layer of a second portion of the fin structure, forming a dielectric layer in the first and second recess structures, and performing an oxygen-free cyclic etching process to etch the dielectric layer to expose the channel layer of the second portion of the fin structure. The oxygen-free cyclic etching process can include two etching processes to selectively etch the dielectric layer over the channel layer.Type: ApplicationFiled: January 2, 2023Publication date: May 11, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Yu LIN, Jhih-Rong HUANG, Yen-Tien TUNG, Tzer-Min SHEN, Fu-Ting YEN, Gary CHAN, Keng-Chu LIN, Li-Te LIN, Pinyen LIN
-
Patent number: 11646234Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.Type: GrantFiled: June 29, 2021Date of Patent: May 9, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
-
Publication number: 20230118700Abstract: A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.Type: ApplicationFiled: December 15, 2022Publication date: April 20, 2023Inventors: Han-Yu Lin, Chansyun David Yang, Tze-Chung Lin, Fang-Wei Lee, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
-
Patent number: 11605728Abstract: A semiconductor device structure is provided. The semiconductor device includes a first nanowire structure over a second nanowire structure, a gate stack wrapping around the first nanowire structure and the second nanowire structure, a source/drain feature adjoining the first nanowire structure and the second nanowire structure, a gate spacer layer over the first nanowire structure and between the gate stack and the source/drain feature, and an inner spacer layer between the first nanowire structure and the second nanowire structure and between the gate stack and the source/drain feature. The gate spacer layer has a first carbon concentration, the inner spacer has a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.Type: GrantFiled: October 18, 2021Date of Patent: March 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Yu Lin, Chansyun David Yang, Fang-Wei Lee, Tze-Chung Lin, Li-Te Lin, Pinyen Lin
-
Publication number: 20230064393Abstract: The present disclosure describes a method that includes forming a fin structure with a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the second semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening and etching a portion of the second semiconductor layer with a fluorine-containing gas through the opening.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tze-Chung LIN, Han-Yu LIN, Fang-Wei LEE, Li-Te LIN, Pinyen LIN
-
Publication number: 20230067696Abstract: A semiconductor device comprising a semiconductor channel, an epitaxial structure coupled to the semiconductor channel, and a gate structure electrically coupled to the semiconductor channel. The semiconductor device further comprises a first interconnect structure electrically coupled to the epitaxial structure and a dielectric layer that contains nitrogen. The dielectric layer comprises a first portion protruding from a nitrogen-containing dielectric capping layer that overlays either the gate structure or the first interconnect structure.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Lien Huang, Yi-Shan Chen, Kuan-Da Huang, Han-Yu Lin, Li-Te Lin, Ming-Huan Tsai
-
Publication number: 20230020731Abstract: The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.Type: ApplicationFiled: November 23, 2021Publication date: January 19, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Yu Lin, Szu-Hua Chen, Kuan-Kan Hu, Kenichi Sano, Po-Cheng Wang, Wei-Yen Woon, Pinyen Lin, Che Chi Shih
-
Publication number: 20230017512Abstract: The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.Type: ApplicationFiled: July 16, 2021Publication date: January 19, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tze-Chung LIN, Pinyen LIN, Fang-Wei LEE, Li-Te LIN, Han-yu LIN
-
Publication number: 20230009745Abstract: A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.Type: ApplicationFiled: July 8, 2021Publication date: January 12, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Ming LIN, Han-Yu LIN, Wei-Yen WOON, Mrunal Abhijith KHADERBAD