Abstract: A method for FinFET fabrication includes forming at least three semiconductor fins over a substrate, wherein first, second, and third of the semiconductor fins are lengthwise substantially parallel to each other, spacing between the first and second semiconductor fins is smaller than spacing between the second and third semiconductor fins; depositing a first dielectric layer over top and sidewalls of the semiconductor fins, resulting in a trench between the second and third semiconductor fins, bottom and two opposing sidewalls of the trench being the first dielectric layer; implanting ions into one of the two opposing sidewalls of the trench by a first tilted ion implantation process; implanting ions into another one of the two opposing sidewalls of the trench by a second tilted ion implantation process; depositing a second dielectric layer into the trench, the first and second dielectric layers having different materials; and etching the first dielectric layer.

Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, where the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.

Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, wherein the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.

Abstract: The current disclosure describes techniques for forming a gate-all-around device where semiconductor layers are released by etching out the buffer layers that are vertically stacked between semiconductor layers in an alternating manner. The buffer layers stacked at different vertical levels include different material compositions, which bring about different etch rates with respect to an etchant that is used to remove at least partially the buffer layers to release the semiconductor layers.

Abstract: In some embodiments, a method is provided. Dummy gate stacks are formed over a semiconductor substrate. An interlayer dielectric (ILD) layer is formed over the dummy gate stacks. A first portion of the ILD layer over top surfaces of the dummy gate stacks is removed, such that a second portion of the ILD layer remains between the dummy gate stacks. The dummy gate stacks are replaced with metal gate stacks. Neutral NF3 radicals into the water are applied to etch the ILD layer.

Abstract: A method of fabricating a semiconductor device includes forming a structure including multiple nanowires vertically stacked above a substrate; depositing a dielectric material layer wrapping around the nanowires; performing a treatment process to a surface portion of the dielectric material layer; selectively etching the surface portion of the dielectric material layer; repeating the steps of performing the treatment process and selectively etching until the nanowires are partially exposed; and forming a gate structure engaging the nanowires.

Abstract: A method for FinFET fabrication includes forming at least three semiconductor fins over a substrate, wherein first, second, and third of the semiconductor fins are lengthwise substantially parallel to each other, spacing between the first and second semiconductor fins is smaller than spacing between the second and third semiconductor fins; depositing a first dielectric layer over top and sidewalls of the semiconductor fins, resulting in a trench between the second and third semiconductor fins, bottom and two opposing sidewalls of the trench being the first dielectric layer; implanting ions into one of the two opposing sidewalls of the trench by a first tilted ion implantation process; implanting ions into another one of the two opposing sidewalls of the trench by a second tilted ion implantation process; depositing a second dielectric layer into the trench, the first and second dielectric layers having different materials; and etching the first dielectric layer.

Abstract: A method for forming a semiconductor device structure is provided. The method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method for forming the semiconductor device structure also includes removing the first semiconductor layers of the fin structure in a channel region thereby exposing the second semiconductor layers of the fin structure. The method for forming the semiconductor device structure also includes forming a dielectric material surrounding the second semiconductor layers, and treating a first portion of the dielectric material. The method for forming the semiconductor device structure also includes etching the first portion of the dielectric material to form gaps, and filling the gaps with a gate stack.

Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, wherein the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.

Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.

Abstract: In some embodiments, a method is provided. Dummy gate stacks are formed over a semiconductor substrate. An interlayer dielectric (ILD) layer is formed over the dummy gate stacks. A first portion of the ILD layer over top surfaces of the dummy gate stacks is removed, such that a second portion of the ILD layer remains between the dummy gate stacks. The dummy gate stacks are replaced with metal gate stacks. Neutral NF3 radicals into the water are applied to etch the ILD layer.

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.