Patents by Inventor Hang Chang

Hang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11192775
    Abstract: A microelectromechanical systems (MEMS) package with roughness for high quality anti-stiction is provided. A device substrate is arranged over a support device. The device substrate comprises a movable element with a lower surface that is rough and that is arranged within a cavity. A dielectric layer is arranged between the support device and the device substrate. The dielectric layer laterally encloses the cavity. An anti-stiction layer lines the lower surface of the movable element. A method for manufacturing the MEMS package is also provided.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: December 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Chang, I-Shi Wang, Jen-Hao Liu
  • Patent number: 11174156
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first wafer comprising a first face and a second face opposite the first face and having a plurality of predetermined die areas. A plurality of recesses are disposed in the first face of the first wafer. A first recess of the plurality of recesses extends in a direction substantially parallel to a first edge of at least one of the plurality of predetermined die areas and laterally surrounds the at least one of the plurality of predetermined die areas. A second wafer is bonded to the second face of the first wafer.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Chang, I-Shi Wang, Jen-Hao Liu
  • Patent number: 10816326
    Abstract: A polarization maintaining fiber array includes a substrate, a cover, and at least two polarization maintaining optical fibers. The substrate includes at least two main grooves, a first additional groove, and a second additional groove, wherein the main grooves are positioned between the first additional groove and the second additional groove. The fiber array includes at least two polarization maintaining optical fibers positioned in the at least two main grooves, a first dummy fiber positioned in the first additional groove, and a second dummy fiber positioned in the second additional groove. The cover is positioned such that it contacts the polarization maintaining optical fibers, the first dummy fiber, and the second dummy fiber.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: October 27, 2020
    Assignee: Alliance Fiber Optic Products, Inc.
    Inventors: Chia-Hang Chang, Ximao Feng, Wen-Lung Kuang, Andy Fenglei Zhou
  • Patent number: 10776606
    Abstract: Embodiments disclosed herein provide methods and systems for delineating cell nuclei and classifying regions of histopathology or microanatomy while remaining invariant to batch effects. These systems and methods can include providing a plurality of reference images of histology sections. A first set of basis functions can then be determined from the reference images. Then, the histopathology or microanatomy of the histology sections can be classified by reference to the first set of basis functions, or reference to human engineered features. A second set of basis functions can then be calculated for delineating cell nuclei from the reference images and delineating the nuclear regions of the histology sections based on the second set of basis functions.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: September 15, 2020
    Assignee: The Regents of the University of California
    Inventors: Bahram Parvin, Hang Chang, Yin Zhou
  • Publication number: 20200243564
    Abstract: A method for repairing a substrate and an electronic device are disclosed, wherein the electronic device includes: a substrate; a patterned metal layer disposed on the substrate, and the patterned metal layer including a first metal section and a second metal section which is disconnected to the first metal section, wherein at least one of the first metal section and the second metal section has a through hole; and a first conductive layer electrically connected to one of the first metal section and the second section by the through hole; wherein the first conductive layer has a protrusion, the protrusion locating outside the through hole.
    Type: Application
    Filed: December 30, 2019
    Publication date: July 30, 2020
    Inventors: Ming-Chuan WANG, Shang-Yen TSAI, Wei-Hang CHANG
  • Publication number: 20200223689
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first wafer comprising a first face and a second face opposite the first face and having a plurality of predetermined die areas. A plurality of recesses are disposed in the first face of the first wafer. A first recess of the plurality of recesses extends in a direction substantially parallel to a first edge of at least one of the plurality of predetermined die areas and laterally surrounds the at least one of the plurality of predetermined die areas. A second wafer is bonded to the second face of the first wafer.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 16, 2020
    Inventors: Chih-Hang Chang, I-Shi Wang, Jen-Hao Liu
  • Patent number: 10626010
    Abstract: A method for forming a semiconductor device structure is provided. The method includes receiving a first wafer having multiple predetermined die areas. The method also includes forming a recess in the first wafer, and the recess extends in a direction substantially parallel to an edge of one of the predetermined die areas. The method further includes receiving a second wafer. In addition, the method includes bonding the first wafer and the second wafer at an elevated temperature after the recess is formed.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hang Chang, I-Shi Wang, Jen-Hao Liu
  • Publication number: 20200096324
    Abstract: A polarization maintaining fiber array includes a substrate, a cover, and at least two polarization maintaining optical fibers. The substrate includes at least two main grooves, a first additional groove, and a second additional groove, wherein the main grooves are positioned between the first additional groove and the second additional groove. The fiber array includes at least two polarization maintaining optical fibers positioned in the at least two main grooves, a first dummy fiber positioned in the first additional groove, and a second dummy fiber positioned in the second additional groove. The cover is positioned such that it contacts the polarization maintaining optical fibers, the first dummy fiber, and the second dummy fiber.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 26, 2020
    Inventors: Chia-Hang Chang, Ximao Feng, Wen-Lung Kuang, Andy Fenglei Zhou
  • Publication number: 20200024125
    Abstract: A microelectromechanical systems (MEMS) package with roughness for high quality anti-stiction is provided. A device substrate is arranged over a support device. The device substrate comprises a movable element with a lower surface that is rough and that is arranged within a cavity. A dielectric layer is arranged between the support device and the device substrate. The dielectric layer laterally encloses the cavity. An anti-stiction layer lines the lower surface of the movable element. A method for manufacturing the MEMS package is also provided.
    Type: Application
    Filed: April 17, 2019
    Publication date: January 23, 2020
    Inventors: Chih-Hang Chang, I-Shi Wang, Jen-Hao Liu
  • Publication number: 20190161344
    Abstract: A method for forming a semiconductor device structure is provided. The method includes receiving a first wafer having multiple predetermined die areas. The method also includes forming a recess in the first wafer, and the recess extends in a direction substantially parallel to an edge of one of the predetermined die areas. The method further includes receiving a second wafer. In addition, the method includes bonding the first wafer and the second wafer at an elevated temperature after the recess is formed.
    Type: Application
    Filed: September 6, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hang CHANG, I-Shi WANG, Jen-Hao LIU
  • Publication number: 20190164929
    Abstract: In an embodiment, a system includes: a circular frame comprising a first side and a second side opposite the first side, wherein the circular frame comprises an aperture formed therethrough; an insert disposed within the aperture; a first wafer disposed over the insert; a second wafer disposed over the first wafer, wherein both the first wafer and the second wafer are configured for eutectic bonding when heated; two clamps disposed on the first side along the circular frame, wherein the two clamps are configured to contact the second wafer at respective clamp locations; and a plurality of pieces configured to secure the insert within the aperture, the plurality of pieces comprising both fixed and flexible pieces, the plurality of pieces comprising two fixed pieces disposed respectively adjacent to the clamp locations along the second side of the circular frame.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 30, 2019
    Inventors: Chih-Hang Chang, Richard Huang, I-Shi Wang, Yin-Tun Chou, Jen-Hao Liu
  • Patent number: 10273141
    Abstract: A microelectromechanical systems (MEMS) package with roughness for high quality anti-stiction is provided. A device substrate is arranged over a support device. The device substrate comprises a movable element with a lower surface that is rough and that is arranged within a cavity. A dielectric layer is arranged between the support device and the device substrate. The dielectric layer laterally encloses the cavity. An anti-stiction layer lines the lower surface of the movable element. A method for manufacturing the MEMS package is also provided.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hang Chang, I-Shi Wang, Jen-Hao Liu
  • Patent number: 10112826
    Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a recess in a first substrate and forming a dielectric layer on the first substrate and in the recess. The method also includes forming a second substrate on the dielectric layer and etching a portion of the second substrate to form a MEMS structure. The MEMS structure has a plurality of openings. The method further includes etching a portion of the dielectric layer to form a cavity below the openings.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hang Chang, Jen-Hao Liu, I-Shi Wang
  • Publication number: 20180148327
    Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a recess in a first substrate and forming a dielectric layer on the first substrate and in the recess. The method also includes forming a second substrate on the dielectric layer and etching a portion of the second substrate to form a MEMS structure. The MEMS structure has a plurality of openings. The method further includes etching a portion of the dielectric layer to form a cavity below the openings.
    Type: Application
    Filed: March 10, 2017
    Publication date: May 31, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hang CHANG, Jen-Hao LIU, I-Shi WANG
  • Publication number: 20170305738
    Abstract: A microelectromechanical systems (MEMS) package with roughness for high quality anti-stiction is provided. A device substrate is arranged over a support device. The device substrate comprises a movable element with a lower surface that is rough and that is arranged within a cavity. A dielectric layer is arranged between the support device and the device substrate. The dielectric layer laterally encloses the cavity. An anti-stiction layer lines the lower surface of the movable element. A method for manufacturing the MEMS package is also provided.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 26, 2017
    Inventors: Chih-Hang Chang, I-Shi Wang, Jen-Hao Liu
  • Patent number: 9748200
    Abstract: A manufacturing method of a wafer level package structure includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an active surface and a back surface opposite to the active surface, and a plurality of pads on the active surface, and the back surface of the chip is adhered to the supporting board through a die attach film (DAF). A molding is disposed on the supporting board to perform a wafer level exposed die molding procedure on the chip, wherein the molding surrounds the chip, and the pads of the chip are exposed out of the molding. A redistribution layer (RDL) is formed on the active surface of the chip, wherein the RDL is electrically connected to the pads. The supporting board and the DAF are removed from the chip.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 29, 2017
    Assignee: Powertech Technology Inc.
    Inventor: Chia-Hang Chang
  • Publication number: 20170229425
    Abstract: A manufacturing method of a wafer level package structure includes the following steps. A chip is disposed on a supporting board, wherein the chip includes an active surface and a back surface opposite to the active surface, and a plurality of pads on the active surface, and the back surface of the chip is adhered to the supporting board through a die attach film (DAF). A molding is disposed on the supporting board to perform a wafer level exposed die molding procedure on the chip, wherein the molding surrounds the chip, and the pads of the chip are exposed out of the molding. A redistribution layer (RDL) is formed on the active surface of the chip, wherein the RDL is electrically connected to the pads. The supporting board and the DAF are removed from the chip.
    Type: Application
    Filed: November 10, 2016
    Publication date: August 10, 2017
    Applicant: Powertech Technology Inc.
    Inventor: Chia-Hang Chang
  • Publication number: 20170225948
    Abstract: A method for fusion bonding a pair of substrates together with silane preconditioning is provided. A surface of a first oxide layer or a surface of a second oxide layer is preconditioned with silane. The first and second oxide layers are respectively arranged on first and second semiconductor substrates. Water is applied to the surface of the first or second oxide layer. The surfaces of the first and second oxide layers are brought in direct contact. The first and second oxide layers are annealed. A method for manufacturing a microelectromechanical systems (MEMS) package using the fusion bonding is also provided.
    Type: Application
    Filed: February 5, 2016
    Publication date: August 10, 2017
    Inventors: Chien-Ning Hsin, I-Shi Wang, Jen-Hao Liu, Chih-Hang Chang
  • Patent number: 9725312
    Abstract: A method for fusion bonding a pair of substrates together with silane preconditioning is provided. A surface of a first oxide layer or a surface of a second oxide layer is preconditioned with silane. The first and second oxide layers are respectively arranged on first and second semiconductor substrates. Water is applied to the surface of the first or second oxide layer. The surfaces of the first and second oxide layers are brought in direct contact. The first and second oxide layers are annealed. A method for manufacturing a microelectromechanical systems (MEMS) package using the fusion bonding is also provided.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Ning Hsin, I-Shi Wang, Jen-Hao Liu, Chih-Hang Chang
  • Patent number: 9625537
    Abstract: The present invention discloses a magnetic field sensing device and method. The magnetic field sensing device includes a pinned layer with a first magnetization direction, an analyzer with a second magnetization direction, wherein the first and the second magnetization directions form an angle, and a sensing layer of magnetic material, located between the analyzer and the pinned layer. The magnetic field sensing method includes: providing a pinned layer with a first magnetization direction, providing an analyzer with a second magnetization direction, wherein the first and the second magnetization directions form an angle, and providing a sensing layer of magnetic material, located between the analyzer and the pinned layer.
    Type: Grant
    Filed: November 29, 2014
    Date of Patent: April 18, 2017
    Inventors: Jui-Hang Chang, Ching-Ray Chang