Patents by Inventor Hang-Ting Lue

Hang-Ting Lue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integration of 3D stacked IC device with peripheral circuits
    Patent number: 8759899
    Abstract: An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: June 24, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Yi-Hsuan Hsiao, Shih-Hung Chen, Yen-Hao Shih
  • NAND flash biasing operation
    Patent number: 8760928
    Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: June 24, 2014
    Assignee: Macronix International Co. Ltd.
    Inventors: Ti-Wen Chen, Hang-Ting Lue, Shuo-Nan Hung, Shih-Lin Huang, Chih-Chang Hsieh, Kuo-Pin Chang
  • MEMORY ARCHITECTURE OF 3D ARRAY WITH DIODE IN MEMORY STRING
    Publication number: 20140141583
    Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 22, 2014
    Applicant: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Shin-Jang Shen, Hang-Ting Lue
  • Thermally assisted flash memory with diode strapping
    Patent number: 8724393
    Abstract: A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: May 13, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Chun-Hsiung Hung
  • Semiconductor structure with improved capacitance of bit line
    Patent number: 8704205
    Abstract: A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 22, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Hang-Ting Lue, Kuang-Yeu Hsieh, Erh-Kun Lai, Yen-Hao Shih
  • One-transistor cell semiconductor on insulator random access memory
    Patent number: 8705278
    Abstract: Silicon-oxide-nitride-oxide-silicon SONOS-type devices (or BE-SONOS) fabricated in Silicon-On-Insulator (SOI) technology for nonvolatile implementations. An ultra-thin tunnel oxide can be implemented providing for very fast program/erase operations, supported by refresh operations as used in classical DRAM technology. The memory arrays are arranged in divided bit line architectures. A gate injection, DRAM cell is described with no tunnel oxide.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: April 22, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • Mask Design With Optically Isolated Via and Proximity Correction Features
    Publication number: 20140078804
    Abstract: A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define vias are positioned on the mask in rows and columns with a row and a column pitch between each row and column on the mask. The via patterns are positioned such that via features that are in adjacent columns are separated by at least one intervening row between them. The via patterns can also be positioned such that the via patterns that are in adjacent rows are separated by at least one intervening column between them. As a result, the via feature of each via pattern and the associated optical proximity correction features that are positioned around each via feature do not overlap with the optical proximity correction features and the via features of the surrounding via patterns.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: Macronix International Co., Ltd.
    Inventors: Chih-Chang Hsieh, Shih-Hung Chen, Hang-Ting Lue
  • Transistor having an adjustable gate resistance and semiconductor device comprising the same
    Patent number: 8675381
    Abstract: A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: March 18, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Kuo-Pin Chang
  • SEMICONDUCTOR STRUCTURE WITH IMPROVED CAPACITANCE OF BIT LINE
    Publication number: 20140054535
    Abstract: A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Hung Chen, Hang-Ting Lue, Kuang-Yeu Hsieh, Erh-Kun Lai, Yen-Hao Shih
  • REDUCED NUMBER OF MASKS FOR IC DEVICE WITH STACKED CONTACT LEVELS
    Publication number: 20140053979
    Abstract: A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2x-1 contact levels are etched for each mask sequence number x, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. Methods create the interconnect contact regions aligned with landing areas at the contact levels.
    Type: Application
    Filed: November 1, 2013
    Publication date: February 27, 2014
    Applicant: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Hang-Ting Lue
  • Memory architecture of 3D array with diode in memory string
    Patent number: 8659944
    Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: February 25, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Shin-Jang Shen, Hang-Ting Lue
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD AND OPERATING METHOD OF THE SAME
    Publication number: 20140043067
    Abstract: A semiconductor structure and a manufacturing method and an operating method of the same are provided. The semiconductor structure includes a substrate, a main body structure, a first dielectric layer, a first conductive strip, a second conductive strip, a second dielectric layer, and a conductive structure. The main body structure is formed on the substrate, and the first dielectric layer is formed on the substrate and surrounding two sidewalls and a top portion of the main body structure. The first conductive strip and the second conductive strip are formed on two sidewalls of the first dielectric layer, respectively. The second dielectric layer is formed on the first dielectric layer, the first conductive strip, and the second conductive strip. The conductive structure is formed on the second dielectric layer.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Hung Chen, Hang-Ting Lue
  • Semiconductor Structure and Method for Manufacturing the Same
    Publication number: 20140035140
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer.
    Type: Application
    Filed: October 9, 2013
    Publication date: February 6, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hang-Ting Lue, Yi-Hsuan Hsiao
  • Memory device, manufacturing method and operating method of the same
    Patent number: 8644077
    Abstract: A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a s tring selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: February 4, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Shih-Hung Chen
  • Semiconductor structure and manufacturing method of the same
    Patent number: 8643078
    Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a base, a stacked structure and a doped layer. The stacked structure is formed on the base, wherein the stacked structure comprises a plurality of conductive strips and a plurality of insulating strips, one of the conductive strips is located between adjacent two insulating strips, the stacked structure has a first side wall, and a long edge of the first side wall is extended along a channel direction. The doped layer is formed in the first side wall, wherein the doped layer is formed by an ion implantation applied to the first side wall, and an acute angle is contained between an implantation direction of the ion implantation and the first side wall.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: February 4, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Hang-Ting Lue, Kuang-Yeu Hsieh
  • Memory architecture of 3D NOR array
    Patent number: 8630114
    Abstract: A 3D memory device includes a plurality of ridge-shaped stacks of memory cells. Word lines are arranged over the stacks of memory cells. Bit lines structures are coupled to multiple locations along the stacks of memory cells. Source line structures are coupled to multiple locations along each of the semiconductor material strips of the stacks. The bit line structures and the source line structures are between adjacent ones of the word lines.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: January 14, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Hang-Ting Lue
  • NAND FLASH BIASING OPERATION
    Publication number: 20130343130
    Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.
    Type: Application
    Filed: December 11, 2012
    Publication date: December 26, 2013
    Inventors: TI-WEN CHEN, HANG-TING LUE, SHUO-NAN HUNG, SHIH-LIN HUANG, CHIH-CHANG HSIEH, KUO-PIN CHANG
  • Damascene Word Line
    Publication number: 20130334575
    Abstract: The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Applicant: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Yen-Hao Shih, Hang-Ting Lue
  • Semiconductor structure and method for manufacturing the same
    Patent number: 8609554
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: December 17, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Yi-Hsuan Hsiao
  • Reduced number of masks for IC device with stacked contact levels
    Patent number: 8598032
    Abstract: A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2x?1 contact levels are etched for each mask sequence number x, x being a sequence number for the masks so that for one mask x=1, for another mask x=2, and so forth through x=N. Methods create the interconnect contact regions aligned with landing areas at the contact levels.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: December 3, 2013
    Assignee: Macronix International Co., Ltd
    Inventors: Shih-Hung Chen, Hang-Ting Lue