Abstract: A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.

Abstract: A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2N contact levels. Each mask is used to etch effectively half of the contact openings. When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls.

Abstract: A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.

Abstract: A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

Abstract: A memory and a manufacturing method thereof are provided. The memory includes a dielectric layer, a polysilicon layer, a first buried diffusion, a second buried diffusion, a charge storage structure and a gate. The polysilicon layer is disposed on the dielectric layer and electrically connected to at least a voltage. The first buried diffusion and the second buried diffusion are separately disposed in the surface of the polysilicon layer. The charge storage structure is disposed on the polysilicon layer and positioned between the first buried diffusion and the second buried diffusion. The gate is disposed on the charge storage structure.

Abstract: A method for operating a semiconductor structure is provided. The semiconductor structure comprises a substrate, a first stacked structure, a dielectric element, a conductive line, a first conductive island and a second conductive island. The first stacked structure is formed on the substrate. The first stacked structure comprises first conductive strips and first insulating strips stacked alternately. The first conductive strips are separated from each other by the first insulating strips. The dielectric element is formed on the first stacked structure. The conductive line is formed on the dielectric element. The first conductive island and the second conductive island on opposite sidewalls of the first stacked structure are separated from each other. The method for operating the semiconductor structure comprises respectively applying a first voltage to the first conductive island and applying a second voltage to the second conductive island.

Abstract: A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking layer of metal doped silicon oxide material having a medium dielectric constant, such as aluminum doped silicon oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric.

Abstract: Various embodiments are directed to 3D memory arrays that lack a select line and devices controlled by the select line between one of the source line and the bit line, and the memory cells. Diodes between the other of source line and the bit line, and the memory cells provide needed isolation from the memory cells.

Abstract: A memory includes an array of memory cells including rows and columns including segmented word lines along the rows. The segments of the segmented word lines include local word lines. First and second switches are coupled to corresponding first and second ends of local word lines. The memory includes circuitry coupled to the first and second switches to connect bias voltages to the local word lines to induce current flow for thermal anneal. The circuitry includes pairs of global word lines along corresponding rows. The pairs of global word lines include first global word lines coupled to the first switches in the local word lines along the corresponding rows, and second global word lines coupled to the second switches in the local word lines along the corresponding rows. The memory includes bit lines along corresponding columns. Bit lines can comprise local bit lines coupled to global bit lines.

Abstract: A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-? material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

Abstract: A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation.

Abstract: A method of performing an operation on a flash memory cell device, used when a gate coupling ratio between a floating gate and a control gate of less than 0.4. A potential is required to be applied across the control gate. Electrons are either injected to the floating gate from the control gate or ejected from the floating gate to the control gate. The operation associated with the injection or the ejection is determined by the nature of a silicon channel provided in the device. Devices using a bulk-tied FinFET-like structure are particularly suited to this method. The method is also particularly suited for use on cells in a NAND array.

Abstract: Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation.

Abstract: A memory includes an array of memory cells including rows and columns. The memory includes circuitry coupled to the word lines applying a first bias voltage to a first set of spaced-apart locations on a word line or word lines in the array, while applying a second bias voltage different than the first bias voltage, to a second set of spaced-apart locations on the word line or word lines, locations in the first set of spaced-apart locations being interleaved among locations in the second set of spaced-apart locations, whereby current flow is induced between locations in the first and second sets of locations that cause heating of the word line or word lines.

Abstract: A memory device includes an array of dielectric charge trapping structures memory cells including word lines and bit lines. Control circuitry is coupled to the array arranged to control read, program and erase operations. A controller is arranged with supporting circuitry thermally annealing charge trapping structures in the memory cells in the array. Word line drivers and word line termination circuits can be used to induce current flow on the word lines to induce heat for the annealing. The thermal annealing can be applied interleaved with normal operations for recover from cycling damage. Also, the thermally annealing can be applied during mission functions like erase, to improve performance of the function.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, a dielectric element, and a conductive line. The first stacked structure and the second stacked structure are disposed on the substrate. Each of the first stacked structure and the second stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is disposed on the first stacked structure and the second stacked structure and includes a second dielectric portion. The first stacked structure and the second stacked structure are separated from each other by only the second dielectric portion. The conductive line is disposed on the stack sidewalls of the first stacked structure and the second stacked structure far from the second dielectric portion.

Abstract: An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.

Abstract: A gate structure for a semiconductor device is provided. The gate structure includes a conductive structure. The conductive structure insulatively disposed over a substrate includes a middle portion and two spacer portions. The middle portion has a first surface and two second surfaces. The first surface is between the two second surfaces. The two spacer portions are respectively connected to the two second surfaces of the middle portion. A width of each of the two spacer portions gradually increases from top to bottom.

Abstract: A diode memory device has an intermediate structure between the two terminals, such as a p terminal and the n terminal.

Abstract: A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process.