Abstract: A buffer circuit is provided to output an output signal at an output node. The buffer circuit includes first and second inverters and first and second switches. The first inverter inverts an input signal. The second inverter is coupled between the first inverter and the output node. The first switch is coupled between a first voltage source terminal and the output node. The second switch is coupled between the output node and a second voltage source terminal. First and second voltages are respectively provided to the first and second voltage source terminals. In response to the input signal switching to a first level from a second level, the first switch is turned on to pre-charge the output node. In response to the input signal transiting to the second level from the first level, the second switch is turned on to pre-discharge the output node.

Abstract: UV curable (meth)acrylate compositions incorporating a thiol-containing component show increased surface reaction conversions and thus have improved, dry to the touch surface cure properties.

Abstract: Methods, systems, and devices for data management are described. In some systems, a client may request for a data management system (DMS) to execute a first instance of a query to obtain, from a database, first information that is responsive to the query. The DMS may identify, in response to the query being executed in an execution time that is greater than a threshold amount of time, an improved version of the query that is associated with a second execution time that is less than the threshold amount of time. The DMS may store the improved version of the query. The DMS may retrieve the improved version of the query in response to receiving a second instance of the query. The DMS may execute the improved version of the query after retrieving the improved version from storage to obtain, from the database, second information that is responsive to the query.

Abstract: An electronic device and method for wireless communication, the method including detecting a beam quality of a currently serving beam; starting a prediction window when the detected beam quality is within a particular range, and evaluating the beam quality of the currently serving beam within the prediction window.

Abstract: An integrated circuit device includes a plurality of selecting modules, wherein each of the plurality of selecting modules is configured to receive a first input signal, a second input signal, a first selecting signal and a second selecting signal, and select the first input signal or the second input signal to generate an output signal according to a first selecting signal and a second selecting signal; and a selecting signal providing module, configured to provide the first selecting signal and the second selecting signal.

Abstract: Methods, systems, and devices for data management are described. In some systems, a client may request for a data management system (DMS) to execute a first instance of a query to obtain, from a database, first information that is responsive to the query. The DMS may identify, in response to the query being executed in an execution time that is greater than a threshold amount of time, an improved version of the query that is associated with a second execution time that is less than the threshold amount of time. The DMS may store the improved version of the query. The DMS may retrieve the improved version of the query in response to receiving a second instance of the query. The DMS may execute the improved version of the query after retrieving the improved version from storage to obtain, from the database, second information that is responsive to the query.

Abstract: A power level detection circuit is provided. The power level detection circuit includes a resistive circuit, a pull-up circuit, a pull-down circuit, and an output terminal. The resistive circuit is coupled between a first power terminal and a first node. The first terminal is coupled to a first supply voltage. The pull-up circuit is coupled between a second power terminal and a second node. The second power terminal is coupled to a second supply voltage. The pull-down circuit is coupled between the second node and a common ground. The output terminal is coupled to the second node and configured to output a detection signal. The pull-up circuit and the pull-down circuit are configured to control a time point that the detection signal starts to transition from a first level to a second level according to the first supply voltage and the second supply voltage.

Abstract: An apparatus and method in a wireless communication system and a computer readable storage medium. The apparatus comprises a processing circuit, which is configured to: configure a sounding reference signal (SRS) mapping structure for a user equipment on the basis of at least the number of antenna ports of the user equipment and the number of transmitting beams and/or receiving beams to be scanned; and notify the user equipment of the SRS mapping structure, wherein the SRS mapping structure at least comprises SRS resource settings for achieving uplink beam management and channel state information (CSI) acquisition at the same time, thereby reducing the system time delay and improving the uplink resource utilization rate.

Abstract: A power management integrated circuit (PMIC) chip for providing power loss protection to an application device. The PMIC chip may be adapted to co-work with a plurality sets of storage capacitors that are charged using power from a power source during normal operation. An application device receives power from the power source during normal operation and receives power from an operational set of storage capacitors during power loss. A failing set of storage capacitors is disconnected from an operational set of storage capacitors and from the PMIC chip. The operational set of storage capacitors remains connected to the PMIC chip to provide power loss protection.

Abstract: The present disclosure discloses a method for extracting parasitic capacitance of interconnection lines of an integrated circuit based on discontinuous Galerkin finite element method.

Abstract: The present disclosure discloses a method for extracting parasitic capacitance of interconnection lines of an integrated circuit based on discontinuous Galerkin finite element method.

Abstract: A register with data retention includes a master-slave flip-flop, a balloon latch, and a level shifter. The master-slave flip-flop is supplied by a first power voltage. The balloon latch is supplied by a second power voltage. The second power voltage is independent of the first power voltage. The level shifter provides a voltage conversion between the master-slave flip-flop and the balloon latch. A data is stored in the master-slave flip-flop. When the first power voltage is disabled, the balloon latch is configured to temporarily retain the data.

Abstract: Adhesive compositions having optical clarity are disclosed. The compositions include saturated epoxy-functionalized compound; a heat cure system which includes an alicyclic anhydride and a cationic catalyst; a predominantly hydrophobic cross-linking (meth)acrylate in amounts sufficient to control the crosslinking density of the composition; and a photoinitiator to allow for initial fixturing of the composition prior to thermal cure. The compositions provide an optical transmittance of at least 95% and a yellowness (*b) of <1%.

Abstract: An expansion joint is provided. The expansion joint is formed from a plurality of layers comprising a ring tie-in ply, a pair of arch rings at opposing transition points, two body plies, with inverted bias cut angles between about 48° to 60°, where about is typically plus or minus 1 degree. The arch geometry is such that the arch has an axial length C between the transition points and an inner surface arch circumference length of A between the transition points in a neutral state, such that the maximum compression distance for the expansion joint is the length C, the maximum elongation distance for the expansion joint is a length (A-C), and a maximum lateral deflection length for the expansion joint is a length Y.

Abstract: A vehicle includes an engine, a clutch, and a controller. The clutch is configured to crank the engine during an engine start. The controller is programmed to, in response to a command to start the engine, adjust a clutch actuator pressure to drive a disconnect clutch torque toward a desired value. The controller is further programmed to, in response to variances of the disconnect clutch torque relative to the clutch actuator pressure exceeding a threshold, issue a disconnect clutch fault.

Abstract: A method of producing a disconnect clutch includes producing a disconnect clutch, configured to selectively connect an engine and an electric machine, such that the disconnect clutch exhibits a clutch transfer function that causes a transmission output shaft torque variability that is less than a predetermined threshold during a simulated starting of the engine using the electric machine.

Abstract: An antibacterial peptide P104 and a lysin LysP53 with broad-spectrum lytic activity and applications thereof are provided. The amino acid sequence of the antibacterial peptide P104 is shown as SEQ ID NO: 1, and the gene sequence of the antibacterial peptide P104 is shown as SEQ ID NO: 3. The amino acid sequence of the lysin LysP53 is shown as SEQ ID NO: 2, and the gene sequence of the lysin LysP53 is shown as SEQ ID NO: 4. The antibacterial peptide P104 and the lysin LysP53 have lytic activity against Gram-negative bacteria, such as Acinetobacter baumannii, Pseudomonas aeruginosa, Klebsiella pneumoniae and Escherichia coli The lysin LysP53 can be subjected to soluble expression by Escherichia coli, and the activity of the lysin is high. Therefore, they have good application prospects in the research and development of anti-infective drugs.

Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.

Abstract: An apparatus and method in a wireless communication system and a computer readable storage medium. The apparatus comprises a processing circuit, which is configured to: configure a sounding reference signal (SRS) mapping structure for a user equipment on the basis of at least the number of antenna ports of the user equipment and the number of transmitting beams and/or receiving beams to be scanned; and notify the user equipment of the SRS mapping structure, wherein the SRS mapping structure at least comprises SRS resource settings for achieving uplink beam management and channel state information (CSI) acquisition at the same time, thereby reducing the system time delay and improving the uplink resource utilization rate.

Abstract: A data processing method and data processing apparatus are provided. The data processing method includes: acquiring multiple input tensors as input parameters for calculation process; for each input tensor, using M input sub-tensors that are combined to represent the input tensor; for each of the input tensors, replacing the input tensors with the M input sub-tensors that are combined to represent the input tensor, and performing the calculation process to obtain a calculation result. The data processing method increases the applicable scenarios of calculation process, effectively utilizes the powerful calculation ability of the originally provided low-accuracy floating points, and greatly improves the overall calculation efficiency.