Patents by Inventor Hang Yang

Hang Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10351593
    Abstract: Derivatives of dolastatin 10 and uses thereof, the structures of which are shown as formula I, II, III and IV are provided.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 16, 2019
    Assignee: NewBio Therapeutics, Inc.
    Inventors: Nianhe Han, Deqiang An, Peng Zhu, Chengyu Hou, Hang Yang, Li Jian, Chun Yang
  • Patent number: 10314922
    Abstract: A type of trimaleimide linkers and uses thereof are disclosed. The trimaleimide linkers can be applied for preparation of antibody-drug conjugate as shown by formula I: L-(T-A-D)n I wherein, L is an antibody, antibody fragment or protein; T is a trimaleimide linker; A is a cleavable linker group or a noncleavable linker; D is a drug; n is an integer ranging from 1 to 8.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: June 11, 2019
    Assignee: NewBio Therapeutics, Inc.
    Inventors: Nianhe Han, Deqiang An, Di Zeng, Baoxiang Wang, Hang Yang, Li Jian, Chun Yang
  • Publication number: 20190173555
    Abstract: Provided in the disclosure are an electronic device and method for a network control terminal, and an electronic device and method for a network node. The electronic device and method for a network control terminal comprise: a processing circuit configured to determine, based on first indication information from an adjacent network control terminal, that a network node served by the present network control terminal measures a channel state information reference signal (CSI RS) port of reference signal receiving power (RSRP) of same, wherein the first indication information indicates an interference state of the CSI RS port used by the corresponding adjacent network control terminal; and determine, based on a measurement result from the network node, the adjacent network control terminal interfering with the network node, and the CSI RS port thereof.
    Type: Application
    Filed: November 3, 2017
    Publication date: June 6, 2019
    Applicant: Sony Corporation
    Inventors: Jin XU, Chaonan HE, Hang YANG, Siqi LIU, Cheng GAO, Jianfei CAO
  • Patent number: 10306664
    Abstract: The present invention relates to a deterministic scheduling method oriented to an industrial wireless WIA-PA network, and belongs to the technical field of industrial wireless network communication. According to the deterministic scheduling method, in middle and small scale WIA-PA networks, a scheduling solution can be obtained using an optimal deterministic scheduling method based on a backtracking method by establishing a solution space tree for data stream scheduling after part or all of the solution space tree is searched, and an optimal success rate of the scheduling can be obtained; and in a large scale WIA-PA network, the time margin of each time slot is calculated for each data stream using a suboptimal deterministic scheduling method based on least slack first, the scheduling is prioritized according to the time margin, and a scheduling solution can be obtained in a short time at a higher success rate.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 28, 2019
    Assignee: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Heng Wang, Ping Wang, Peng Fei Chen, Hang Yang
  • Patent number: 10297587
    Abstract: An integrated circuit is provided. In one implementation, the integrated circuit includes a first standard cell, comprising at least one first PMOS transistor disposed in a first row in a semiconductor substrate and at least one first NMOS transistor disposed in a first area of a second row in the semiconductor substrate, and a second standard cell, comprising a plurality of second PMOS transistors disposed in the first row and a third row in the semiconductor substrate and a plurality of second NMOS transistors disposed in a second area of the second row in the semiconductor substrate, wherein the second row is adjacent to the first and third rows and arranged between the first and third rows.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 21, 2019
    Assignee: MEDIATEK INC.
    Inventor: Jen-Hang Yang
  • Publication number: 20180375500
    Abstract: A scan output flip-flop is provided. The scan output flip-flop outputs a scan-out signal at a first output terminal and includes a selection circuit, a control circuit, and a scan-out stage circuit. The selection circuit is controlled by a first test enable signal to transmit a data signal on a first input terminal or a test signal on a second input terminal to an output terminal of the selection circuit to serve as an input signal. The control circuit is coupled to the output terminal of the selection circuit and controlled by a first clock signal to generate a first control signal and a second control signal according to the input signal. The second control signal is the inverse of the first control signal. The scan-out stage circuit is controlled by the first control signal and the second control signal to generate the scan-out signal.
    Type: Application
    Filed: June 27, 2017
    Publication date: December 27, 2018
    Inventors: Min-Hang HSIEH, Wei-Min HSU, Jen-Hang YANG
  • Publication number: 20180291357
    Abstract: The present invention discloses a lysin that is capable of killing Staphylococcus and the use thereof, belonging to the field of biological agents. The present invention discloses the amino acid sequence and the encoding gene sequence of the lysin. This lysin keeps active in a wide range of pH. It has lytic activity against Staphylococcus in pH 4-11. The recombinant protease constructed by the encoding gene can be solubly expressed in E. coli strain BL21 (DE3). The lysin can be used to effectively kill multiple species Staphylococcus in vitro, including methicillin sensitive Staphylococcus aureus (MSSA) and methicillin resistant Staphylococcus aureus (MRSA) isolated in clinics. This lysin can be used as an antibiotic for the treatment of staphylococcal infections in vivo. This lysin is also able to rapidly lyse staphylococcal cell wall; as a result, intracellular substances such as ATP and DNA are released. Those released substances can be used to detect the type of Staphylococcus.
    Type: Application
    Filed: April 12, 2016
    Publication date: October 11, 2018
    Applicant: Wuhan Phagelux Bio-tech Company Limited
    Inventors: Hongping Wei, Hang Yang, Junping Yu
  • Publication number: 20180211750
    Abstract: A three-dimensional inductance coil and a method for producing the same in printed circuit board are provided.
    Type: Application
    Filed: August 11, 2015
    Publication date: July 26, 2018
    Applicant: AKM ELECTRONICS INDUSTRIAL (PANYU) LTD.
    Inventors: Jing Wang, Simeng Zhu, Ling Wang, Hang Yang
  • Publication number: 20180176936
    Abstract: The present invention relates to a deterministic scheduling method oriented to an industrial wireless WIA-PA network, and belongs to the technical field of industrial wireless network communication. According to the deterministic scheduling method, in middle and small scale WIA-PA networks, a scheduling solution can be obtained using an optimal deterministic scheduling method based on a backtracking method by establishing a solution space tree for data stream scheduling after part or all of the solution space tree is searched, and an optimal success rate of the scheduling can be obtained; and in a large scale WIA-PA network, the time margin of each time slot is calculated for each data stream using a suboptimal deterministic scheduling method based on least slack first, the scheduling is prioritized according to the time margin, and a scheduling solution can be obtained in a short time at a higher success rate.
    Type: Application
    Filed: July 1, 2016
    Publication date: June 21, 2018
    Inventors: Heng WANG, Ping WANG, Peng Fei CHEN, Hang YANG
  • Patent number: 9993532
    Abstract: This invention discloses a lysin that can kill many species of Streptococci. A new lysin, ClyR, was constructed by the gene splicing method. The ClyR can effectively kill different species of Streptococci, including Streptococcus pneumoniae, Streptococcus pyogenes, Streptococcus suis, Streptococcus uberis, Streptococcus agalactiae, Streptococcus dysgalactiae, Streptococcus mutans, Streptococcus equi, and various Enterococci and Staphylococcus aureus. ClyR shows good stability and is not sensitive to EDTA and high concentration of NaCl. Moreover, the ClyR is active in a wide range of pH and maintains high activity in pH 5-11. Recombinant protein ClyR is well expressed in E. coli stain BL21 (DE3). High doses of ClyR showed no apparent toxicity in mice. Furthermore, administration of 0.8 mg per mouse once is able to completely protect the mouse infected with lethal doses of Group B Streptococci.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 12, 2018
    Assignee: Wuhan Phagelux Bio-Tech Company Limited
    Inventors: Hongping Wei, Hang Yang, Jing Wang, Junping Yu
  • Publication number: 20180147295
    Abstract: A type of trimaleimide linkers and uses thereof are disclosed. The trimaleimide linkers can be applied for preparation of antibody-drug conjugate as shown by formula I: L-(T-A-D)nI wherein, L is an antibody, antibody fragment or protein; T is a trimaleimide linker; A is a cleavable linker group or a noncleavable linker; D is a drug; n is an integer ranging from 1 to 8.
    Type: Application
    Filed: May 17, 2016
    Publication date: May 31, 2018
    Inventors: Nianhe HAN, Deqiang AN, Di ZENG, Baoxiang WANG, Hang YANG, Li JIAN, Chun YANG
  • Publication number: 20180141973
    Abstract: Derivatives of dolastatin 10 and uses thereof, the structures of which are shown as formula I, II, III and IV are provided.
    Type: Application
    Filed: May 17, 2016
    Publication date: May 24, 2018
    Inventors: Nianhe HAN, Deqiang AN, Peng ZHU, Chengyu HOU, Hang YANG, Li JIAN, Chun YANG
  • Publication number: 20180104316
    Abstract: This invention discloses a lysin that can kill many species of Streptococci. A new lysin, ClyR, was constructed by the gene splicing method. The ClyR can effectively kill different species of Streptococci, including Streptococcus pneumoniae, Streptococcus pyogenes, Streptococcus suis, Streptococcus uberis, Streptococcus agalactiae, Streptococcus dysgalactiae, Streptococcus mutans, Streptococcus equi, and various Enterococci and Staphylococcus aureus. ClyR shows good stability and is not sensitive to EDTA and high concentration of NaCl. Moreover, the ClyR is active in a wide range of pH and maintains high activity in pH 5-11. Recombinant protein ClyR is well expressed in E. coli stain BL21 (DE3). High doses of ClyR showed no apparent toxicity in mice. Furthermore, administration of 0.8 mg per mouse once is able to completely protect the mouse infected with lethal doses of Group B Streptococci.
    Type: Application
    Filed: April 12, 2016
    Publication date: April 19, 2018
    Applicant: Wuhan Phagelux Bio-Tech Company Limited
    Inventors: Hongping Wei, Hang Yang, Jing Wang, Junping Yu
  • Publication number: 20170365594
    Abstract: An integrated circuit is provided. In one implementation, the integrated circuit includes a first standard cell, comprising at least one first PMOS transistor disposed in a first row in a semiconductor substrate and at least one first NMOS transistor disposed in a first area of a second row in the semiconductor substrate, and a second standard cell, comprising a plurality of second PMOS transistors disposed in the first row and a third row in the semiconductor substrate and a plurality of second NMOS transistors disposed in a second area of the second row in the semiconductor substrate, wherein the second row is adjacent to the first and third rows and arranged between the first and third rows.
    Type: Application
    Filed: September 7, 2017
    Publication date: December 21, 2017
    Inventor: Jen-Hang YANG
  • Patent number: 9786645
    Abstract: An integrated circuit is provided. A standard cell includes a plurality of PMOS transistors and a plurality of NMOS transistors. The PMOS transistors are disposed in a first row and a second row in the semiconductor substrate. The NMOS transistors are disposed in a third row in the semiconductor substrate. The third row is adjacent to the first and second rows and arranged between the first and second rows.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: October 10, 2017
    Assignee: MEDIATEK INC.
    Inventor: Jen-Hang Yang
  • Patent number: 9704167
    Abstract: Service management methods for use in an electronic device are provided, including the steps of: providing a record including at least one first event and possible probability parameters corresponding thereto, each having a weight; collecting device status information regarding information of current status of the electronic device, user operation behavior information and event triggering information using a data collector; evaluating a first evaluation value according to the device status information regarding information of current status of the electronic device, user operation behavior information and event triggering information, the possible probability parameters and respective weights of the record; and inferring that the first event reoccurs and performing a service corresponding to the first event when the first evaluation value has exceeded a threshold value.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: July 11, 2017
    Assignee: ACER INCORPORATED
    Inventors: Tsung-Hang Yang, Shu-Han Wang, Yu-Hsiang Wu, Ling-Fan Tsao
  • Patent number: 9705484
    Abstract: A delay cell for generating a desired delay exceeding a minimum delay defined in a standard cell library is provided, which includes a delay element and an output inverter. The delay element receives an input signal to generate an internal signal with a propagation delay relative to the input signal, which includes a P-type transistor, a first resistor, a second resistor, and an N-type transistor. The P-type transistor applies a supply voltage to the first resistor by the input signal. The first resistor is coupled between the P-type transistor and the output inverter. The second resistor is coupled to the output inverter and coupled to the ground through the N-type transistor by the input signal. The output inverter receives the internal signal to generate an output signal with the desired delay, which is dominated by the propagation delay, relative to the input signal.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 11, 2017
    Assignee: MEDIATEK INC.
    Inventors: Ying-Chun Wei, Jen-Hang Yang
  • Publication number: 20170036369
    Abstract: A splitting apparatus of an LCD panel and splitting method thereof are described. The LCD panel has a first substrate and a second substrate. The splitting apparatus includes a first splitting device and a second splitting device disposed correspondingly to the first splitting device, and the second splitting device includes protrusion adjustment devices. The protrusion adjustment device extrudes the second substrate for forming a protrusion corresponding to a split line to separate a split plate from the first substrate by a deformation portion of the protrusion and to remove the split plate by the first splitting device. The splitting apparatus makes a rapid separation of the split plate.
    Type: Application
    Filed: October 19, 2016
    Publication date: February 9, 2017
    Inventors: Dong Li, Hang Yang, Haibo Huang
  • Patent number: 9536031
    Abstract: A replacement method for scan cell of an integrated circuit (IC) is provided. A gate-level netlist of the IC is obtained. A place-and-route process is performed on the gate-level netlist to obtain a first netlist. A clock tree synthesis process is performed on the first netlist to obtain a second netlist. Static timing analysis is performed to analyze a plurality of first scan cells of the second netlist in normal mode and scan mode. The first scan cell is replaced with a second scan cell according to the static timing analysis that indicates the replaced first scan cell has a specific time margin in the scan mode. A first skew of the normal mode and a second skew of the scan mode are adjusted symmetrically in the first scan cell. The first skew and the second skew are adjusted asymmetrically in the second scan cell.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: January 3, 2017
    Assignee: MEDIATEK INC.
    Inventors: Jen-Yi Liao, Jen-Hang Yang
  • Publication number: 20160380624
    Abstract: A delay cell for generating a desired delay exceeding a minimum delay defined in a standard cell library is provided, which includes a delay element and an output inverter. The delay element receives an input signal to generate an internal signal with a propagation delay relative to the input signal, which includes a P-type transistor, a first resistor, a second resistor, and an N-type transistor. The P-type transistor applies a supply voltage to the first resistor by the input signal. The first resistor is coupled between the P-type transistor and the output inverter. The second resistor is coupled to the output inverter and coupled to the ground through the N-type transistor by the input signal. The output inverter receives the internal signal to generate an output signal with the desired delay, which is dominated by the propagation delay, relative to the input signal.
    Type: Application
    Filed: April 26, 2016
    Publication date: December 29, 2016
    Inventors: Ying-Chun WEI, Jen-Hang YANG