Patents by Inventor Han-Gu Kim
Han-Gu Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240147636Abstract: A display device includes: a panel assembly including a display panel; a bracket to which the panel assembly is attached; and a buffer layer between the panel assembly and the bracket, and the buffer layer includes: a first portion having a first elastic modulus; and a second portion surrounded by the first portion and having a second elastic modulus that is less than the first elastic modulus.Type: ApplicationFiled: January 2, 2024Publication date: May 2, 2024Inventors: Dong Jin PARK, Han Sun RYOU, Min Gu KIM
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Publication number: 20240124077Abstract: A vehicle configured for container-swapping, includes: a main frame including a pair of drive modules spaced in a forward/backward direction of the vehicle, and a connecting portion extending in the forward/backward direction of the vehicle to connect the pair of drive modules so that a coupling space is formed therebetween; a container module selectively inserted into the coupling space of the main frame; and a coupling portion configured to couple the main frame and the container to each other while the container module is inserted into the coupling space of the main frame, wherein a driving portion operates and moves the main frame so that the container module is inserted into the coupling space of the main frame.Type: ApplicationFiled: May 8, 2023Publication date: April 18, 2024Applicants: Hyundai Motor Company, Kia CorporationInventors: Dong Eun CHA, Han Sam KIM, Tae Kyung LEE, Dae Hee LEE, Jin Ho HWANG, Jun Gu LEE, Sang Heon LEE
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Patent number: 11952652Abstract: Provided is a method of manufacturing a zinc-plated steel sheet. The method includes: coating a metal on the steel sheet on a steel sheet; annealing the metal coated steel sheet; and zinc plating the annealed steel sheet by dipping in a molten zinc plating bath. Further provided is a method of manufacturing a hot-press part including: coating a metal on the steel sheet on a steel sheet; annealing the metal coated steel sheet; zinc plating the annealed steel sheet by dipping in a molten zinc plating bath; heating the zinc-plated steel sheet; and press forming the heated steel sheet.Type: GrantFiled: March 7, 2018Date of Patent: April 9, 2024Assignee: POSCO CO., LTDInventors: Il-Ryoung Sohn, Jong-Sang Kim, Joong-Chul Park, Yeol-Rae Cho, Jin-Keun Oh, Han-Gu Cho, Bong-Hoon Chung, Jong-Seog Lee
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Patent number: 11108229Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a transient-state detection circuit configured to generate a dynamic triggering signal based on a voltage change rate of a voltage on a first power rail; a voltage detection circuit configured to generate a static triggering signal based on the voltage on the first power rail; a trigger circuit configured to generate a discharge control signal based on the dynamic triggering signal and the static triggering signal; and a main discharge circuit configured to discharge an electric charge from the first power rail to a second power rail based on the discharge control signal.Type: GrantFiled: July 18, 2018Date of Patent: August 31, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Pil Jang, Chang-Su Kim, Han-Gu Kim, Moon-Seok Yang, Kyoung-Ki Jeon
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Patent number: 10488452Abstract: A test board for a semiconductor device and a test board including the same are provided. A test board includes a substrate, a mounting pad which is formed on the substrate and on which a semiconductor chip is mounted and a test terminal group arranged on the substrate to be spaced apart from the mounting pad and electrically connected to the semiconductor chip by a pattern arranged on the substrate, wherein the semiconductor chip includes a first terminal and a second terminal for inputting/outputting signals, the test terminal group includes a first test terminal electrically connected to the first terminal and a second test terminal electrically connected to the second terminal, a first voltage is applied to the first terminal and the second terminal, and a stress signal that is caused by a second voltage is applied to the first test terminal.Type: GrantFiled: December 15, 2016Date of Patent: November 26, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Jun Song, Young Min Kim, Chang Su Kim, Han Gu Kim
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Patent number: 10318678Abstract: A three-dimensional optoelectrical simulation includes generating a process simulation result including a doping profile of a silicon substrate of image sensor, a structure simulation result with respect to a back end of line structure, and a merged result generated by merging a process simulation result and a structure simulation result, selectively extending the merged result to an extended result by using a process simulation result or a structure simulation result, generating a segmented result for each pixel based on a merged result or an extended result, an optical crosstalk simulation result of image sensor based on a structure simulation result and an optical mesh, and a final simulation result including an electrical crosstalk simulation result of the image sensor based on a segmented result for each pixel and an optical crosstalk simulation result.Type: GrantFiled: April 16, 2014Date of Patent: June 11, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Wook Lee, Han-Gu Kim, Young-Keun Lee, Jong-Sung Jeon
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Publication number: 20190173278Abstract: An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a transient-state detection circuit configured to generate a dynamic triggering signal based on a voltage change rate of a voltage on a first power rail; a voltage detection circuit configured to generate a static triggering signal based on the voltage on the first power rail; a trigger circuit configured to generate a discharge control signal based on the dynamic triggering signal and the static triggering signal; and a main discharge circuit configured to discharge an electric charge from the first power rail to a second power rail based on the discharge control signal.Type: ApplicationFiled: July 18, 2018Publication date: June 6, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Pil JANG, Chang-Su KIM, Han-Gu KIM, Moon-Seok YANG, Kyoung-Ki JEON
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Patent number: 10211196Abstract: An electrostatic discharge (ESD) protection device includes an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor including a source electrode, a gate electrode, and a well bias electrode that are connected to a first pad receiving a first voltage, and a drain electrode connected to a middle node. The ESD protection device further includes a silicon controlled rectifier (SCR) connected between the middle node and a second pad receiving a second voltage higher than the first voltage.Type: GrantFiled: August 11, 2016Date of Patent: February 19, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Hyok Ko, Min-Chang Ko, Han-Gu Kim, Jong-Kyu Song, Jin Heo
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Patent number: 10134723Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.Type: GrantFiled: September 19, 2017Date of Patent: November 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Hyok Ko, Han-Gu Kim, Jong-Kyu Song, Jin Heo
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Patent number: 10121776Abstract: A film-type semiconductor package includes a semiconductor integrated circuit and a dummy metal pattern. The semiconductor integrated circuit is formed on a film and includes an electrostatic discharge (ESD) protection circuit. The dummy metal pattern is formed on the film and is electrically connected to the ESD protection circuit through a first wiring formed on the film.Type: GrantFiled: November 30, 2016Date of Patent: November 6, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Jun Song, Young-Min Kim, Chang-Su Kim, Han-Gu Kim
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Patent number: 10020231Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.Type: GrantFiled: February 27, 2017Date of Patent: July 10, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-Hee Jeon, Eun-Kyoung Kwon, Il-Ryong Kim, Han-Gu Kim, Woo-Jin Seo, Ki-Tae Lee
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Publication number: 20180012883Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.Type: ApplicationFiled: September 19, 2017Publication date: January 11, 2018Inventors: Jae-Hyok Ko, Han-Gu Kim, Jong-Kyu Song, Jin Heo
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Patent number: 9799641Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.Type: GrantFiled: July 27, 2015Date of Patent: October 24, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hyok Ko, Han-Gu Kim, Jong-Kyu Song, Jin Heo
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Publication number: 20170176508Abstract: A test board for a semiconductor device and a test board including the same are provided. A test board includes a substrate, a mounting pad which is formed on the substrate and on which a semiconductor chip is mounted and a test terminal group arranged on the substrate to be spaced apart from the mounting pad and electrically connected to the semiconductor chip by a pattern arranged on the substrate, wherein the semiconductor chip includes a first terminal and a second terminal for inputting/outputting signals, the test terminal group includes a first test terminal electrically connected to the first terminal and a second test terminal electrically connected to the second terminal, a first voltage is applied to the first terminal and the second terminal, and a stress signal that is caused by a second voltage is applied to the first test terminal.Type: ApplicationFiled: December 15, 2016Publication date: June 22, 2017Inventors: Sung Jun SONG, Young Min KIM, Chang Su KIM, Han Gu KIM
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Publication number: 20170170166Abstract: A film-type semiconductor package includes a semiconductor integrated circuit and a dummy metal pattern. The semiconductor integrated circuit is formed on a film and includes an electrostatic discharge (ESD) protection circuit. The dummy metal pattern is formed on the film and is electrically connected to the ESD protection circuit through a first wiring formed on the film.Type: ApplicationFiled: November 30, 2016Publication date: June 15, 2017Inventors: SUNG-JUN SONG, YOUNG-MIN KIM, CHANG-SU KIM, HAN-GU KIM
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Publication number: 20170170075Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.Type: ApplicationFiled: February 27, 2017Publication date: June 15, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Chan-Hee JEON, Eun-Kyoung KWON, II-Ryong KIM, Han-Gu KIM, Woo-Jin SEO, Ki-Tae LEE
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Patent number: 9620502Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.Type: GrantFiled: February 12, 2014Date of Patent: April 11, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-Hee Jeon, Eun-Kyoung Kwon, Il-Ryong Kim, Han-Gu Kim, Woo-Jin Seo, Ki-Tae Lee
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Publication number: 20170062406Abstract: An electrostatic discharge (ESD) protection device includes an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor including a source electrode, a gate electrode, and a well bias electrode that are connected to a first pad receiving a first voltage, and a drain electrode connected to a middle node. The ESD protection device further includes a silicon controlled rectifier (SCR) connected between the middle node and a second pad receiving a second voltage higher than the first voltage.Type: ApplicationFiled: August 11, 2016Publication date: March 2, 2017Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-Hyok KO, Min-Chang KO, Han-Gu KIM, Jong-Kyu SONG, Jin HEO
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Publication number: 20160163690Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.Type: ApplicationFiled: July 27, 2015Publication date: June 9, 2016Inventors: Jae-Hyok Ko, Han-Gu Kim, Han-Gu Kim, Jong-Kyu Song, Jin Heo
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Patent number: 9270105Abstract: A semiconductor apparatus that includes: a first high-voltage transistor having a gate and a first electrode, wherein the first electrode is connected to a first pad and a parasitic capacitance forms between the gate and the first electrode; and a clamping circuit that is connected to the gate of the first high-voltage transistor, wherein the clamping circuit detects a change in a level of a gate voltage of the first high-voltage transistor due to electrostatic discharge, and clamps the gate voltage of the first high-voltage transistor according to a result of the detection.Type: GrantFiled: September 3, 2013Date of Patent: February 23, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jae-hyok Ko, Woo-seok Kim, Han-gu Kim, Sang-young Cho