Patents by Inventor Hans CHUANG

Hans CHUANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230090030
    Abstract: A nano-twinned structure on a metallic thin film surface is provided. The nano-twinned structure includes a substrate, an adhesive-lattice-buffer layer over the substrate, and a metallic thin film including Ag, Cu, Au, Pd or Ni over the adhesive-lattice-buffer layer. The bottom region of the metallic thin film has equi-axial coarse grains. The surface region of the metallic thin film contains parallel-arranged high-density twin boundaries (?3+?9) with a pitch from 1 nm to 100 nm. The quantity of the parallel-arranged twin boundaries is 50% to 80% of the total quantity of twin boundaries in the cross-sectional view of the metallic thin film. The parallel-arranged twin boundaries include 30% to 90% [111] crystal orientation. The nano-twinned structure on the metallic thin film surface is formed through a post-deposition ion bombardment on the evaporated metallic thin film surface after the evaporation process.
    Type: Application
    Filed: June 6, 2022
    Publication date: March 23, 2023
    Inventors: Tung-Han CHUANG, Po-Ching WU, Pei-Ing LEE, Hsing-Hua TSAI
  • Publication number: 20230065208
    Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.
    Type: Application
    Filed: August 31, 2021
    Publication date: March 2, 2023
    Inventors: Tsung-Han CHUANG, Zhi-Chang LIN, Shih-Cheng CHEN, Jung-Hung CHANG, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20230057312
    Abstract: A metallic nano-twinned thin film structure and a method for forming the same are provided. The metallic nano-twinned thin film structure includes a substrate, an adhesive-lattice-buffer layer over the substrate, and a single-layer or multi-layer metallic nano-twinned thin film over the adhesive-lattice-buffer layer. The metallic nano-twinned thin film includes parallel-arranged twin boundaries (?3+?9). In a cross-sectional view of the metallic nano-twinned thin film, the parallel-arranged twin boundaries account for 30% to 90% of total twin boundaries. The parallel-arranged twin boundaries include 80% to 99% of crystal orientation [111]. The single-layer metallic nano-twinned thin film includes copper, gold, palladium or nickel. The multi-layer metallic nano-twinned thin films are respectively composed of silver, copper, gold, palladium or nickel.
    Type: Application
    Filed: September 28, 2021
    Publication date: February 23, 2023
    Inventors: Tung-Han CHUANG, Po-Ching WU, Pei-Ing LEE, Hsing-Hua TSAI
  • Publication number: 20230027664
    Abstract: A bonding structure is provided, including a first substrate; a second substrate disposed opposite the first substrate; a first bonding layer disposed on the first substrate; a second bonding layer disposed on the second substrate and opposite the first bonding layer; and a silver feature disposed between the first bonding layer and the second bonding layer. The silver feature includes a silver nano-twinned structure including parallel twin boundaries. The silver nano-twinned structure includes 90% or more [111] crystal orientation. A method for forming a bonding structure is also provided. Each of steps of forming a first silver feature and second silver feature includes sputtering or evaporation coating. Negative bias ion bombardment is applied to the first silver feature and second silver feature during sputtering or evaporation.
    Type: Application
    Filed: March 18, 2022
    Publication date: January 26, 2023
    Inventors: Tung-Han CHUANG, Hsing-Hua TSAI
  • Publication number: 20230028900
    Abstract: An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source/drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.
    Type: Application
    Filed: March 11, 2022
    Publication date: January 26, 2023
    Inventors: Zhi-Chang LIN, Chien Ning YAO, Shih-Cheng CHEN, Jung-Hung CHANG, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20220416036
    Abstract: A device includes a substrate. A first channel region of a first transistor overlies the substrate and a source/drain region is in contact with the first channel region. The source/drain region is adjacent to the first channel region along a first direction, and the source/drain region has a first surface opposite the substrate and side surfaces extending from the first surface. A dielectric fin structure is adjacent to the source/drain region along a second direction that is transverse to the first direction, and the dielectric fin structure has an upper surface, a lower surface, and an intermediate surface that is disposed between the upper and lower surfaces. A silicide layer is disposed on the first surface and the side surfaces of the source/drain region and on the intermediate surface of the dielectric fin structure.
    Type: Application
    Filed: January 14, 2022
    Publication date: December 29, 2022
    Inventors: Shih-Cheng CHEN, Zhi-Chang LIN, Jung-Hung CHANG, Chien-Ning YAO, Tsung-Han CHUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20220388092
    Abstract: A method for forming a bonding structure is provided, including providing a first metal, wherein the first metal has a first absolute melting point. The method includes forming a silver nano-twinned layer on the first metal. The silver nano-twinned layer includes parallel-arranged twin boundaries. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation. The method includes oppositely bonding the silver nano-twinned layer to a second metal. The second metal has a second absolute melting point. The bonding of the silver nano-twinned layer and the second metal is performed at a temperature of 300° C. to half of the first absolute melting point or 300° C. to half of the second absolute melting point.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 8, 2022
    Inventors: Tung-Han CHUANG, Po-Ching WU, Pei-Ing LEE, Yu-Chang LAI, Hsing-Hua TSAI, Chung-Hsin CHOU
  • Publication number: 20220359975
    Abstract: An electronic package is provided, in which a ground layer is arranged on one side of an insulator, and a first antenna portion and a second antenna portion embedded in the insulator are vertically disposed on the ground layer, where a gap is formed between the first antenna portion and the second antenna portion, such that the first antenna portion and the second antenna portion are electrically matched with each other, and the ground layer is electrically connected to the second antenna portion but free from being electrically connected to the first antenna portion.
    Type: Application
    Filed: June 28, 2021
    Publication date: November 10, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Chu Lai, Ho-Chuan Lin, Min-Han Chuang
  • Publication number: 20220359324
    Abstract: An electronic package is provided, in which an electronic component with a conductive layer on an outer surface thereof is embedded in an encapsulant, where at least one electrode pad is disposed on an active surface of the electronic component, and at least one wire electrically connected to the electrode pad is arranged inside the electronic component, so that the conductive layer is electrically connected to the wire, such that the electrode pad, the wire and the conductive layer are used as a power transmission structure which serves as a current path to reduce DC resistance and improve an impedance issue associated with the supply of power.
    Type: Application
    Filed: July 6, 2021
    Publication date: November 10, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ho-Chuan Lin, Min-Han Chuang, Chia-Chu Lai
  • Publication number: 20220359374
    Abstract: An electronic module is provided, in which a first metal layer, an insulating layer and a second metal layer are sequentially formed on side faces and a non-active face of an electronic component to serve as a capacitor structure, where the capacitor structure is exposed from an active face of the electronic component so that by directly forming the capacitor structure on the electronic component, a distance between the capacitor structure and the electronic component is minimized, such that the effect of suppressing impedance can be optimized.
    Type: Application
    Filed: September 2, 2021
    Publication date: November 10, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Ho-Chuan Lin, Chia-Chu Lai, Min-Han Chuang
  • Patent number: 11484136
    Abstract: A portable reusable utensil is provided that includes an upper casing, a lower casing, and a utensil body. The utensil body is mounted in a receiving space formed between the upper casing and the lower casing detachably connected to each other for storage and easy to carry. While in use, a service end of the utensil body is facing outwards while an assembly of the upper casing and the lower casing is used as a part held with user's hand to serve food. The design makes the portable reusable utensil more convenient to use.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: November 1, 2022
    Assignee: Yuan Min Metal Technology Co., Ltd.
    Inventor: Ming-Han Chuang
  • Publication number: 20220344298
    Abstract: A bonding structure is provided, wherein the bonding structure includes a first substrate, a second substrate, a first adhesive layer, a second adhesive layer, and a silver feature. The second substrate is disposed opposite to the first substrate. The first adhesive layer is disposed on the first substrate. The second adhesive layer is disposed on the second substrate and opposite the first adhesive layer. The silver feature is disposed between the first adhesive layer and the second adhesive layer. The silver feature includes a silver nano-twinned structure that includes twin boundaries that are arranged in parallel. The parallel-arranged twin boundaries include 90% or more [111] crystal orientation.
    Type: Application
    Filed: August 27, 2021
    Publication date: October 27, 2022
    Inventors: Tung-Han CHUANG, Hsing-Hua TSAI
  • Publication number: 20220336407
    Abstract: A die bonding structure is provided. The die bonding structure includes a chip, an adhesive layer under the chip, a bonding layer under the adhesive layer, and a heat dissipation substrate under the bonding layer. The bonding layer includes a silver nano-twinned thin film, which has parallel-arranged twin boundaries. The parallel-arranged twin boundaries include at least 90% of [111] crystal orientation.
    Type: Application
    Filed: September 13, 2021
    Publication date: October 20, 2022
    Inventors: Tung-Han CHUANG, Hsing-Hua TSAI
  • Publication number: 20220336275
    Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
  • Patent number: 11458533
    Abstract: A measuring device includes a furnace, a draining vessel, a loader and a computing system for physical properties. The draining vessel with molten metal fluid is in the furnace. The loader accumulates the molten metal fluid from the draining vessel. The computing system includes a recording unit, transform unit, computing unit and processor. The recording unit records the vessel information. By the assumed physical parameters and the vessel information, the transform unit transforms a weight of the molten metal fluid in the loader into a first length criterion, and the computing unit simulates the flowing of the molten metal fluid to have a second length criterion. The processor minimizes the difference of the first and the second length criterion by changing the assumed physical parameters. The physical properties of the molten metal fluid are determined when the difference is minimized.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: October 4, 2022
    Assignee: National Central University
    Inventors: Chih-Ang Chung, Ya-Huan Lee, Tsung-Han Chuang, Tsung-Hsuan Chiang, Chih-Shan Yen, Jeng-Rong Ho, Jason Shian-Ching Jang
  • Publication number: 20220223548
    Abstract: Methods for forming under-bump metallurgy (UBM) structures having different surface profiles and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a first under-bump metallurgy (UBM) structure over and electrically coupled to the first redistribution line, the first UBM structure extending through the first passivation layer, a top surface of the first UBM structure being concave; and a second UBM structure over and electrically coupled to the second redistribution line, the second UBM structure extending through the first passivation layer, a top surface of the second UBM structure being flat or convex.
    Type: Application
    Filed: June 9, 2021
    Publication date: July 14, 2022
    Inventors: Ting-Li Yang, Po-Hao Tsai, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang
  • Patent number: 11387143
    Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Da Cheng, Wen-Hsiung Lu, Chin Wei Kang, Yung-Han Chuang, Lung-Kai Mao, Yung-Sheng Lin
  • Publication number: 20220102269
    Abstract: Methods for forming dummy under-bump metallurgy structures and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution line and a second redistribution line over a semiconductor substrate; a first passivation layer over the first redistribution line and the second redistribution line; a second passivation layer over the first passivation layer; a first under-bump metallurgy (UBM) structure over the first redistribution line, the first UBM structure extending through the first passivation layer and the second passivation layer and being electrically coupled to the first redistribution line; and a second UBM structure over the second redistribution line, the second UBM structure extending through the second passivation layer, the second UBM structure being electrically isolated from the second redistribution line by the first passivation layer.
    Type: Application
    Filed: March 26, 2021
    Publication date: March 31, 2022
    Inventors: Ting-Li Yang, Po-Hao Tsai, Ming-Da Cheng, Yung-Han Chuang, Hsueh-Sheng Wang
  • Patent number: 11264231
    Abstract: A method for manufacturing a backside metalized compound semiconductor wafer includes the steps of: providing a compound semiconductor wafer; attaching the compound semiconductor wafer to a supporting structure; forming an adhesion layer including nickel and vanadium on a back surface of the compound semiconductor wafer; forming an alloy layer including titanium and tungsten on the adhesion layer; forming a metallization layer including gold on the alloy layer; and removing the supporting structure from the compound semiconductor wafer to obtain the backside metalized compound semiconductor wafer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: March 1, 2022
    Assignee: Xiamen Sanan Integrated Circuit Co., Ltd.
    Inventors: Tsung-Te Chiu, Bing-Han Chuang, Houng-Chi Wei
  • Publication number: 20220054344
    Abstract: An exoskeleton robotic equipment for tenodesis grasp and release training includes an exoskeleton mechanism and a control device. The exoskeleton mechanism includes a fixing seat worn on a forearm, an actuating device mounted to the fixing seat, and a transmission module connected to the fixing seat and pivotally connected to the actuating device and cooperating with the fixing seat and the actuating device to form a four-bar linkage mechanism. The actuating device is controlled by the control device to drive the transmission module to move relative to the fixing seat to change the transmission module into a release state and into a grasp state so as to move the index finger and the middle finger away from and toward the thumb.
    Type: Application
    Filed: June 4, 2021
    Publication date: February 24, 2022
    Inventors: Hsiu-Yun HSU, Chien-Hsien YEH, Kang-Chin YANG, Ping-Han CHUANG