Abstract: Packet flows between a transmitter and a receiver in an unreliable and unordered switched packet network may be established as a result of receiving a second packet comprising a second memory operation on a memory address. The transmission of memory load command packets followed by memory store command packets in the packet flow may be serialized, and a synchronization operation may be executed between the transmitter and the receiver when a packet count at the receiver satisfies a number of data packets in the packet flow.

Abstract: Packet flows between a transmitter and a receiver in an unreliable and unordered switched packet network may be established as a result of receiving a second packet comprising a second memory operation on a memory address. The transmission of memory load command packets followed by memory store command packets in the packet flow may be serialized, and a synchronization operation may be executed between the transmitter and the receiver when a packet count at the receiver satisfies a number of data packets in the packet flow.

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

Abstract: A network processor is described. This network processor determines a context for a message based on information in one or more fields in a payload of the message. For example, the context may be based on a message type and an identifier of the network connection on which the message was received. Then, the network processor calculates one or more trigger values based on one or more trigger expressions that perform checks on the information in the one or more fields. Moreover, the network processor determines one or more actions to be taken for the message based on the context and the one or more trigger values. In particular, the network processor determines whether the message is forwarded and one or more forwarding destinations.

Abstract: A compression first in, first out (cFIFO) that includes at least two FIFOs is described. A first FIFO is used to store instances of higher words in data entries, and a second FIFO is used to store corresponding instances of lower words in the data entries. If an instance of the higher word for a data entry has a different value than an immediately preceding stored instance of the higher word associated with at least an immediately preceding data entry which is stored in the second FIFO, memory pointers are incremented so that a subsequent instance of the higher word will be stored in the second FIFO without overwriting the instance of the higher word. Otherwise, the memory pointers are unchanged, which associates the instance of the lower word with the immediately preceding stored instance of the higher word.

Abstract: The disclosed embodiments relate techniques for using annotations to extract parameters from messages. During operation, a computing device receives a message from a network interface. After determining a message type for the message, a format decoder in the computing device uses the message type to determine an annotation that is associated with the message type. The message and the annotation are then output to one or more functional units of the computing device, with the annotation output aligned with the message on a per-message-byte basis.

Abstract: A hardware-implemented rate limiter is described. This implementation guarantees that messages containing a value v are not forwarded at a higher rate than a predefined threshold value r. More specifically, given a number of times x in a time interval y, which specifies a rate r defined by x/y, the rate limiter reports a violation by selectively setting an error value when v occurs more than x times during the time interval y. Moreover, the rate limiter may be able to keep track of multiple predefined threshold values for different rates. Furthermore, the rate limiter may keep track of 2b different values v, where b is the number of digits of the binary representation of v.

Abstract: A compression first in, first out (cFIFO) that includes at least two FIFOs is described. A first FIFO is used to store instances of higher words in data entries, and a second FIFO is used to store corresponding instances of lower words in the data entries. If an instance of the higher word for a data entry has a different value than an immediately preceding stored instance of the higher word associated with at least an immediately preceding data entry which is stored in the second FIFO, memory pointers are incremented so that a subsequent instance of the higher word will be stored in the second FIFO without overwriting the instance of the higher word. Otherwise, the memory pointers are unchanged, which associates the instance of the lower word with the immediately preceding stored instance of the higher word.

Abstract: A hardware-implemented rate limiter is described. This implementation guarantees that messages containing a value v are not forwarded at a higher rate than a predefined threshold value r. More specifically, given a number of times x in a time interval y, which specifies a rate r defined by x/y, the rate limiter reports a violation by selectively setting an error value when v occurs more than x times during the time interval y. Moreover, the rate limiter may be able to keep track of multiple predefined threshold values for different rates. Furthermore, the rate limiter may keep track of 2b different values v, where b is the number of digits of the binary representation of v.

Abstract: A network processor is described. This network processor determines a context for a message based on information in one or more fields in a payload of the message. For example, the context may be based on a message type and an identifier of the network connection on which the message was received. Then, the network processor calculates one or more trigger values based on one or more trigger expressions that perform checks on the information in the one or more fields. Moreover, the network processor determines one or more actions to be taken for the message based on the context and the one or more trigger values. In particular, the network processor determines whether the message is forwarded and one or more forwarding destinations.

Abstract: The disclosed embodiments describe single-instruction processors that operates upon messages received from a network interface. A single-instruction processor comprises a register file, a functional unit, a bus connecting the register file and the functional unit, and a format decoder that receives messages from a network interface. This single-instruction processor supports a single instruction type (e.g., a “move instruction”) that specifies operands to be transferred via the bus. During operation, the format decoder is configured to write a parameter from a received message to the register file. A move instruction moves this parameter from the register file to the functional unit via the bus. The functional unit then uses the parameter to perform an operation.

Abstract: The disclosed embodiments describe single-instruction processors that operates upon messages received from a network interface. A single-instruction processor comprises a register file, a functional unit, a bus connecting the register file and the functional unit, and a format decoder that receives messages from a network interface. This single-instruction processor supports a single instruction type (e.g., a “move instruction”) that specifies operands to be transferred via the bus. During operation, the format decoder is configured to write a parameter from a received message to the register file. A move instruction moves this parameter from the register file to the functional unit via the bus. The functional unit then uses the parameter to perform an operation.

Abstract: The disclosed embodiments relate techniques for using annotations to extract parameters from messages. During operation, a computing device receives a message from a network interface. After determining a message type for the message, a format decoder in the computing device uses the message type to determine an annotation that is associated with the message type. The message and the annotation are then output to one or more functional units of the computing device, with the annotation output aligned with the message on a per-message-byte basis.

Abstract: Embodiments of a system that includes a switch and a buffer-management technique for storing signals in the system are described. In this system, data cells are dynamically assigned from a host buffer to at least a subset of switch-ingress buffers in the switch based at least in part on the occupancy of the switch-ingress buffers. This buffer-management technique may reduce the number of switch-ingress buffers relative to the number of input and output ports to the switch, which in turn may overcome the limitations posed by the amount of memory available on chips, thereby facilitating large switches.