Abstract: A switch contains a first semiconductor die, which is configured to receive signals on a plurality of input ports and to output the signals on a plurality of output ports. The first semiconductor die is further configured to selectively couple the signals between the input and output ports using a plurality of switching elements in accordance with a set of control signals, which correspond to a configuration of the switch. During this process, a plurality of proximity connectors, proximate to a surface of the semiconductor die, are configured to communicate the signals by capacitive coupling.

Abstract: A reduction operation is utilized in an arithmetic operation on two binary polynomials X(t) and Y(t) over GF(2), where an irreducible polynomial Mm(t)=tm+am?1tm?1+am?2tm?2+ . . . +a1t+a0, where the coefficients ai are equal to either 1 or 0, and m is a field degree. The reduction operation includes partially reducing a result of the arithmetic operation on the two binary polynomials to produce a congruent polynomial of degree less than a chosen integer n, with m?n. The partial reduction includes using a polynomial M?=(Mm(t)?tm)*tn?m, or a polynomial M?=Mm(t)*tn?m as part of reducing the result to the degree less than n and greater than or equal to m. The integer n can be the data path width of an arithmetic unit performing the arithmetic operation, a multiple of a digit size of a multiplier performing the arithmetic operation, a word size of a storage location, such as a register, or a maximum operand size of a functional unit in which the arithmetic operation is performed.

Abstract: A computer system coupled with a pipelined network includes a plurality of initiator nodes coupled to send packets into the network. A plurality of target nodes receive packets sent into the network. The network uses a plurality of pipeline stages to transmit data across the network. Each pipeline stage consumes a known time period, which provides for a predetermined time period for transmission for each packet that is successfully sent from one of the initiator nodes to one of the target nodes. The pipelined network is synchronous in that boundaries of all the pipeline stages are aligned. The pipeline stages include at least an arbitration stage to obtain a path through the network, a transfer stage during which a data packet is transmitted, and an acknowledge stage during which successful transmission of a packet is indicated by the target. To simplify network design, all the pipeline stages are implemented to have equal length.

Abstract: A data network provides independent transmission channels for transmitting high bandwidth and low latency information data packets between nodes. The data information packets are organized into at least two groups of data packets according to predetermined criteria. The predetermined criteria includes a latency budget of the data packets, the size of the data packets and the type of operation. The low latency channel is also coupled to transmit control information relating to network protocol.

Abstract: Multiple multicast acknowledgements can be merged into a single multicast acknowledgement, thus reducing traffic and reducing logic complexity. An intermediate node that receives multiple multicast acknowledgements merges the multiple acknowledgements into a single acknowledgement, and then supplies the single merged acknowledgment to the multicast source. Encoding of the single merged acknowledgement conveys to the source which of the multicast targets successfully received (or which failed to receive) the multicast information.

Abstract: A system includes a plurality of resources and a plurality of requesters. A first portion of the resources are reserved for a particular time period in the system during a first arbitration phase, in response to prescheduling requests. During a second arbitration phase a second portion of the resources are allocated in response to regular requests, the first portion of the resources which are reserved being unavailable to the regular requests.

Abstract: A distributed arbiter prioritizes requests for resources based on the number of requests made by each requester. Each resource gives the highest priority to servicing requests made by the requester that has made the fewest number of requests. That is, the requester with the fewest requests (least number of choices) is chosen first. Resources may be scheduled sequentially or in parallel. If a requester receives multiple grants from resources, the requester may select a grant based on resource priority, which is inversely related to the number of requests received by a granting resource. In order to prevent starvation, a round robin scheme may be used to allocate a resource to a requester, prior to issuing grants based on requester priority.

Abstract: A source multicasts information to a plurality of targets. The targets respond to the multicast information by sending acknowledgements that indicate receipt of the multicast information. The acknowledgements are merged into a merged acknowledgment, which is then supplied to the source. The source can determine from the merged acknowledgement whether the targets successfully received the multicast information.

Abstract: A switched network includes a buffer-less switch coupling the sending nodes and the receiving nodes. The switch transmits packets successfully delivered to the receiving nodes through the buffer-less switch with a fixed forwarding rate. The switched network resolves conflicts in requests for a transmission path on the switch from multiple packets by allocating the transmission path to a first requester in time for the transmission path. If multiple requests for a switch resource collide by requesting the switch resource at the same time, one of the requests is selected as a winner and the packet or packets associated with the remaining requests are dropped. The winning packet may be selected on a random basis or a round robin basis or based on some other criteria. The requests from transmission paths may be contained with the packets sent into the network and extracted on entry of the packet into the network.

Abstract: In a system with multiple requesters making multiple requests for resources, an arbiter prioritizes requests based on the number of requests made by a requester. The highest priority is given to a requester that has made the fewest number of requests. Priority may instead be based on the number of requests made for a particular resource. Priority may also be based on a combination of number of requests made by a requester and number of requests made for a resource. The arbiter may also implement a starvation avoidance mechanism such as a round robin scheme.

Abstract: In response to executing a single arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is added implicitly to generate a result that represents the first number multiplied by the second number summed with the partial result from a previously executed single arithmetic instruction. The high order portion of the generated result is saved in an extended carry register as a next partial result for use with execution of a subsequent single arithmetic instruction. Execution of a single arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number.

Abstract: In response to executing an arithmetic instruction, a first number is multiplied by a second number, and a partial result from a previously executed single arithmetic instruction is fed back from a first carry save adder structure generating high order bits of the current arithmetic instruction to a second carry save adder tree structure being utilized to generate low order bits of the current arithmetic instruction to generate a result that represents the first number multiplied by the second number summed with the high order bits from the previously executed arithmetic instruction. Execution of the arithmetic instruction may instead generate a result that represents the first number multiplied by the second number summed with the partial result and also summed with a third number, the third number being fed to the carry save adder tree structure.

Abstract: A prefetching technique for a network interface is provided to give the network interface the opportunity to prefetch data out-of-order into send queues in the network interface, rather than prefetching data in the order produced and deposited into main memory. That allows, the state of the send queues to be taken into consideration when deciding an appropriate order to prefetch data.

Abstract: Modular multiplication of two elements X(t) and Y(t), over GF(2), where m is a field degree, may utilize field degree to determine, at least in part, the number of iterations. An extra shift operation may be employed when the number of iterations is reduced. Modular multiplication of two elements X(t) and Y(t), over GF(2), may include a shared reduction circuit utilized during multiplication and reduction. In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm.

Abstract: An apparatus multiplies a first and a second binary polynomial X(t) and Y(t) over GF(2), where an irreducible polynomial Mm(t)=tm+am−1tm−1+am−2tm−2tm−2+ . . . +a1t+a0, and where the coefficients ai are equal to either 1 or 0, and m is a field degree. The degree of X(t)<n, and the degree of Y(t)<n, and m≦n. The apparatus includes a digit serial modular multiplier circuit coupled to supply a multiplication result of degree ≧m of a multiplication of the first and second binary polynomials. The digit serial modular multiplier circuit includes a first and second register, each being ≦n bits. A partial product generator circuit multiplies a portion of digit size d of contents of the first register and contents of the second register. The partial product generator is also utilized as part of a reduction operation for at least one generic curve.

Abstract: A reduction operation is utilized in an arithmetic operation on two binary polynomials X(t) and Y(t) over GF(2), where an irreducible polynomial Mm(t)=tm+am−1tm−1+am−2tm−2+ . . . +a1t+a0, where the coefficients as are equal to either 1 or 0, and m is a field degree. The reduction operation includes partially reducing a result of the arithmetic operation on the two binary polynomials to produce a congruent polynomial of degree less than a chosen integer n, with m≦n. The partial reduction includes using a polynomial M′=(Mm(t)−tm)*tn−m, or a polynomial M″=Mm(t)*tn−m as part of reducing the result to the degree less than n and greater than or equal to m.

Abstract: An elliptic curve processing apparatus that performs operations on elliptic curves specified over binary polynomial fields includes a functional unit that has a digit serial multiplier with a digit size of at least two bits. The elliptic curve processing apparatus performs reduction for respective generic curves using arbitrary irreducible polynomials, which correspond to respective ones of the generic curves. The elliptic curve processing apparatus may include hardwired reduction circuits in the functional unit for use with respective named curves. A storage location in the elliptic curve processing apparatus may be used to specify whether an operation is for one of the named curves or for one of the generic curves.

Abstract: An arbiter is used so multiple users can use shared resources. The arbiter allocates at least one of the resources speculatively to one of the users for use during a particular access interval in the absence of a request for the resource from the user. The arbiter can also allocate one or more of the resources for use during the particular access interval in response to requests received by the arbiter for the resource(s). That is, a particular access interval may include both speculative and non-speculative allocation of resources by the arbiter.

Abstract: A memory module for storing data. The memory module includes: a circuit board that has a plurality of electrical terminals; a volatile memory device that is mounted on the circuit board; and a radio transmitter that is mounted on the circuit board. The radio transmitter is operable to transmit information.

Abstract: One embodiment of the present invention provides a system that facilitates communicating between integrated circuit devices within a computing system. The system includes integrated circuit devices with an individual radio port coupled to each integrated circuit device. Each radio port includes a transmitting mechanism that is configured to generate radio signals in response to commands from the integrated circuit device. An antenna is coupled to the radio port to transmit the radio signal generated by the transmitting mechanism and to detect a response to the radio signal. Each radio port also includes a receiving mechanism to receive responses from the antenna and pass the responses to the integrated circuit device.