Abstract: A marine bioproduction facility for farming of sessile marine organisms in a body of water is disclosed. The facility comprises an array of at least two production modules in contiguous geometrical relationship to each other, where each of the at least two production modules is adapted to be arranged within a vertical column with a predefined horizontal cross section and extending downwards from the water surface, where at least one of the at least two production modules comprises at least one growth surface for sessile marine organisms, and an upper part comprising at least one opening adapted to allow access to the vertical column. Further, a method for growth and harvesting of marine sessile organisms using the marine bioproduction facility is presented.

Abstract: A modular structure for being at least partly submerged in a body of water, is disclosed. The modular structure comprises structure elements and strengthening elements providing structural integrity and flexibility, and can typically be a closed structure like e.g. a tank structure. Further, macro structures comprising attached modular structures are presented. Finally, methods for construction of such structures are disclosed.

Abstract: In a non-volatile electric memory system a memory unit and a read/write unit are provided as physically separate units. The memory unit is based on a memory material that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrodes and/or contacts are either provided in the memory unit or in the read/write unit and contacts are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected. The memory material of the memory unit can be polarized into two discernible polarization states.

Abstract: In a non-volatile electric memory system a memory unit (4) and a read/write unit (11) are provided as physically separate units. The memory unit (10) is based on a memory material (4) that can be set to at least two distinct physical states by applying an electric field across the memory material. Electrode means and/or contact means are either provided in the memory unit or in the read/write unit and contact means are at least always provided in the read/write unit. Electrodes and contacts are provided in a geometrical arrangement, which defines geometrically one or more memory cells in the memory layer. Contact means in the read/write unit are provided connectable to driving, sensing and control means located in the read/write unit or in an external device connected with the latter. Establishing a physical contact between the memory unit and the read/write unit closes an electrical circuit over the addressed memory cell such that read, write or erase operations can be effected.

Abstract: In a method for obviating the effect of disturb voltages in a data storage apparatus employing passive matrix addressing, an application of electric potentials for an addressing operation is according to a voltage pulse protocol. The data storage cells of the apparatus are provided in two or more electrically separated segments each constituting non-overlapping physical address subspaces of the data storage apparatus physical address space. A number of data storage cells in each segment are preset to the same polarization by an active voltage pulse with a specific polarization. In a first addressing operation one or more data storage cells are read by applying an active pulse with the same polarization to each data storage cell and recording the output charge response. On basis thereof the output data in subsequent second addressing operation are copied onto preset data storage cells in another segment of the data storage apparatus, this segment being selected on the basis of its previous addressing history.

Abstract: In a method for reducing detrimental phenomena related to disturb voltages in a data storage apparatus employing passive matrix addressing, particularly a memory device or a sensor device, an application of electric potentials conforming to an addressing operation is generally controlled in a time-coordinated manner according to a voltage pulse protocol. In an addressing operation a data storage cell is set to a first polarization state by means of a first active voltage pulse and then, dependent on the voltage pulse protocol, a second voltage pulse which may be a second active voltage pulse of opposite polarity to that of the first voltage pulse, is applied and used for switching the data storage cell to a second polarization state. The addressed cell is thus set to a predetermined polarization state as specified by the addressing operation.

Abstract: In a method for enhancing the data storage capability of ferroelectric or electret memory cell which has been applied to storage of data and attained an imprint condition, suitable voltage pulses are used for evoking a temporary relaxation of the imprint condition into a volatile polarization state that can be discriminated from the imprinted polarization state in a non-destructive readout operation. Sequences of one or more voltage pulses are used to evoke readout signals respectively indicative of a non-volatile and a volatile polarization state of the memory cell, but without altering said polarization states.

Abstract: An organic electronic device consists of one or more electro-active organic or polymer materials sandwiched between electrodes. Critical in such devices is the interface between the electrode and the polymer, where degradation or chemical reaction products may develop that are deleterious to the proper functioning of the device. This is solved by introducing a functional interlayer composed of one or more materials consisting of a molecular backbone bearing phosphonate or phosphate functions, either directly attached or through side chains, said functional layer being disposed between at least one of the respective electrodes and said one or more electro-active materials in the device.

Abstract: In a heating and temperature control system for a data storage apparatus comprising at least one matrix-addressable ferroelectric or electret memory device, Joule heating means are provided in the memory device, a temperature determining means is connected with controller circuitry and the controller circuitry is connected with an external power supply, which controlled by the former powers the Joule heating means to achieve a selected operating temperature. In a method for operating the heating and temperature control system an ambient or instant temperature of the memory device is determined and compared with the set nominal optimal temperature, and the difference between these temperatures is used in a predefined algorithm for establishing control parameters for the application of power to the Joule heating means to achieve the selected operating temperature in the memory device during an addressing operation thereto.

Abstract: In a method for operating a passive matrix-addressable ferroelectric or electret memory device, a voltage pulse protocol based on a 1/3 voltage selection rule is used in order to keep disturb voltages at minimum, the voltage pulse protocol comprising cycles for read and write/erase bases on time sequence of voltage pulses with defined parameters. The method comprises a refresh procedure wherein cells for refresh are selected and refresh requests processed by a memory device controller, the refresh requests are monitored and processed in regard of ongoing or scheduled memory operations, and refresh voltage pulses with defined parameters are applied to the memory cells selected for refresh, while simultaneously ensuring that non-selected memory cells are subjected to zero voltage or voltages which do not affect the polarization state of these cells.

Abstract: In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwiched self-supporting structure, wherein the layers include memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers the are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind includes the steps for adding the layers successively, one layer at a time, such that the layers form a staggered structure, and for providing one or more layers with at least one electrical contact pad for linking to one or more interlayer edge connectors.

Abstract: In a ferroelectret or electret memory cell a polymeric memory material is a blend of two or more polymeric materials, the polymeric material being provided contacting first and second electrodes. Each electrode is a composite multilayer having a first highly conducting layer and a conducting polymer layer, the latter forming a contact between the former and the memory material.

Abstract: In a volumetric data storage apparatus comprising a plurality of stacked matrix-addressable memory devices electrode means are provided so as to form alternating word and bit line means for the memory devices, whereby the number of the electrode means is only one more than the number of memory devices. Moreover adjoining electrode means are arranged in such a manner as to furnish a high proportion of memory cells which can be switched in two or more directions, thus yielding a much higher output when addressed and having an improved signal-to-noise ratio. Each memory device can, due to having a dense electrode arrangement, be provided with an attainable memory cell fill factor approaching unity and half the memory cells can in case be provided switchable in two or more directions, such that the fill factor of these in any case shall approach 0.5.

Abstract: A method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array.

Abstract: A matrix-addressable ferroelectric or electret memory device and a method of operating are explained. The method includes applying a first plurality of voltage difference across a first and a second set of electrodes in the memory when data are read, and applying a second plurality of voltage differences when data are refreshed or rewritten. The first and second plurality of voltage differences correspond to sets of potential levels comprising time sequences of voltage pulses. At least one parameter indicative of a change in a memory cell response is used for determining at least one correction factor for the voltage pulses, whereby the pulse parameter is adjusted accordingly. The memory device comprises means for determining the at least one parameter, a calibration memory connected with means for determining the correction factor, and control circuits for adjusting pulse parameters as applied to read and write operations in the memory device.

Abstract: In a method for determining the logic state of memory cells in a passive matrix-addressable data storage device with word and bit lines, components of current response are detected and correlated with a probing voltage, and a time-dependent potential is applied on selected word and bit lines or groups thereof, said potentials being mutually coordinated in magnitude and time such that the resulting voltages across all or some of the non-addressed cells at the crossing points between inactive word lines and active bit lines are brought to contain only negligible voltage components that are temporally correlated with the probing voltage. A first apparatus according to the invention for performing the method provides sequential readout of all memory cells on an active word line (AWL) by means of detection circuits (3; 4). An active word line (AWL) is selected by a multiplexer (7), while inactive word lines (IWL) are clamped to ground during readout.

Abstract: A scaleable integrated data processing device, particularly a microcomputer, comprises a processing unit with one or more processors and a storage unit with one or more memories. The data processing device is provided on a carrier substrate (S) and comprises mutually adjacent substantially parallel layers (P, M, MP) stacked up on each other, the processing unit and the storage unit being provided in one or more such layers and the separate layers formed with a selected number of processors and memories in selected combinations. In each layer are provided horizontal electrical conducting structures which constitute electrical internal connections in the layer and besides each layer comprises further electrical conducting structures which provide electrical connections to other layers and to the exterior of the data processing device. The integrated data processing device has a scaleable architecture, such that it in principle can be configured with an almost unlimited processor and memory capacity.

Abstract: A ferroelectric or electret memory circuit, particularly a ferroelectric or electret memory circuit with improved fatigue resistance, including a ferroelectric or electret memory cell with a polymer or oligomer memory material contacting first and second electrodes, at least one of the electrodes is comprised of at least one functional material capable of physical and/or chemical bulk incorporation of atomic or molecular species contained in either the electrode or the memory material and displaying a propensity for migrating in the form of mobile charged and/or neutral particles between an electrode and a memory material, something which can be detrimental to both. A functional material with the above-mentioned properties shall serve to offset any adverse effect of a migration of this kind, leading to an improvement in the fatigue resistance of the memory cell.

Abstract: In a non-volatile memory device that includes an electrically polarizable dielectric memory material with ferroelectric or electret properties and capable of exhibiting hysteresis and remanence, wherein the memory material includes one or more polymers, at least one of these polymers is a deuterated polymer.

Abstract: In an electrode means comprising a first and a second thin-film electrode layers (L1, L2) with electrodes (&egr;) in the form of parallel strip-like electrical conductors in each layer, the electrodes (&egr;) are provided only separated by a thin film (6) of an electrically insulating material with a thickness at most a fraction of the width of the electrodes and at least extending along the side edges thereof and forming an insulating wall (6a) therebetween. The electrode layers (L1, L2) are planarized to obtain an extremely planar surface. In an apparatus comprising one or more electrode means (EM), the electrode layers (L1, L2) of each are mutually oriented with their respective electrodes (1;2) crossing at an angle, preferably orthogonally and with a functional medium (3) provided globally in sandwich therebetween, such that a preferably passive matrix-addressable apparatus is obtained and suited for use as e.g.