Abstract: In a ferroelectric or electret volumetric memory device with a memory material provided in sandwich between first and second electrode layers (2;4) with stripe-like electrodes forming word lines (2) and bit lines (4) of a matrix-addressable memory array (M), memory cells are defined in volumes of memory material in between two crossing word lines (2) and bit lines (4) and a plurality of memory arrays are provided in a stacked arrangement. A stack (S) of memory arrays (M) is formed by two or more ribbon-like structures (R), which are folded and/or braided into each other. Each ribbon-like structure (R) comprises a flexible substrate (3) of non-conducting material and the electrode layers (2;4) provided on each surface of the substrate and comprising the parallel strip-like electrodes extending along the ribbon-like structure (R).

Abstract: In an array of integrated transistor/memory structures the array comprises one or more layers (1) of semiconducting material, two or more electrode layers, and memory material (11) contacting electrodes (2,6,10) in the latter. At least one layer of a semiconducting material and two electrode layers form transistor structures such that the electrodes of the first electrode layer forms source/drain electrode pairs and those of a second electrode layer form the gate electrodes thereof. The source and drain electrodes (2;6) of a single transistor/memory structure are separated by a narrow recess (3) extending down to the semiconducting (1) layer wherein the transistor channel (8) is provided beneath the recess and with extremely small width, while the source and drain regions are provided beneath the respective source and drain electrodes (2;6) on either side of the transistor channel (8). Memory material (11) is provided in the recess (3) and contacts the electrodes (2,6,10) of the transistor.

Abstract: In an electrode means comprising a first and a second thin-film electrode layers (L1,L2) with electrodes (∈) in the form of parallel strip-like electrical conductors in each layer, the electrodes (∈) are provided only separated by a thin film (6) of an electrically insulating material with a thickness at most a fraction of the width of the electrodes and at least extending along the side edges thereof and forming an insulating wall (6a) therebetween. The electrode layers (L1,L2) are planarized to obtain an extremely planar surface. In an apparatus comprising one or more electrode means (EM), the electrode layers (L1,L2) of each are mutually oriented with their respective electrodes (1;2) crossing at an angle, preferably orthogonally and with a functional medium (3) provided globally in sandwich therebetween, such that a preferably passive matrix-addressable apparatus is obtained and suited for use as e.g.

Abstract: In a matrix-addressable apparatus comprising one or more memory devices with multidirectionally switchable memory cells (5) arranged in a passive matrix-addressable array, the memory cells comprise a memory medium in the form of a ferroelectric or electret thin-film memory material capable of being polarized by an applied electric field and exhibiting hysteresis, and preferably the memory material is a polymer or copolymer. A memory device in the apparatus comprises at least a first and a second electrode means (E1;E2) such that the electrodes (&egr;2) of the second electrode means (E2) are provided in recesses (3) in the electrodes (&egr;1) of the first electrode means (E1) and oriented orthogonally thereto, the recesses (3) extending only half-way through the electrodes (&egr;1) of the first electrode means (E1).

Abstract: In a method for making transistors with ultrashort channel length, the deposition of respectively source, drain and gate electrodes initially can be performed with prior art technology limiting the electrode dimensions according to applicable design rules, while the dimensions of every second of these electrodes in subsequent process steps can be adjusted as desired. A channel area is formed between a source and a drain electrode without being constrained by any design rule and this allows the formation of transistor channels with extremely short channel lengths L, e.g. well below 10 nm. Correspondingly the width of the gate electrodes can be adjusted to also obtain a large channel width W and hence provide transistors with almost arbitrarily large aspect ratios W/L and thus desirable switching and current characteristics. The method can be applied to make any kind of field-effect transistor, even on the same substrate and may be adjusted for the fabrication of other kinds of transistor structures as well.

Abstract: A method for generating electrically conducting and/or semiconducting structures in three dimensions in a matrix that includes two or more materials in spatially separated material structures is disclosed. An electric field is applied to the separate material structure and the field is modulated spatially according to a protocol. The protocol represents a predetermined pattern of electrically conducting and/or semiconducting structures that are generated in the material structure in response to the field. The matrix composed by the material structures includes structures of this kind in three dimensions.

Abstract: In a non-volatile memory device (10) comprising an electrically polarizable dielectric memory material (11) with ferroelectric or electret properties and capable of exhibiting hysteresis and remanence, wherein the memory material (11) comprises one or more polymers, at least one of these polymers is a deuterated polymer.

Abstract: In a scalable data processing apparatus, particularly a data storage apparatus, one or more thin-film devices which form a substantially planar layer comprise a plurality of sublayers of thin film. Two or more thin-film devices are provided as an integrated stack of the substantially planar layers which form the thin-film devices, such that the apparatus thereby forms a stacked configuration. Each thin-film device comprises one or more memory areas which form matrix addressable memories and additionally circuit areas which form electronic thin-film circuitry for controlling, driving and addressing memory cells in one or more memories. Each memory device has an interface to every other thin-film device in the apparatus, said interfaces being realized with communication and signal lines as well as supporting circuitry for processing extending vertically through dedicated interface areas in the thin-film device.

Abstract: In a ferroelectric data processing device for processing and/or storage of data with passive or electrical addressing a data-carrying medium is used in the form of a thin film (1) of ferroelectric material which by an applied electric field is polarized to determined polarization states or switched between these and is provided as a continuous layer in or adjacent toelectrode structures in the form of a matrix. A logic element (4) is formed at the intersection between an x electrode (2) and a y electrode (3) of the electrode matrix. The logic element (4) is addressed by applying to the electrodes (2, 3) a voltage greater than the coercivity field of the ferroelectric material.

Abstract: A method for generating electrically conducting and/or semiconducting structures in three dimensions in a matrix that includes two or more materials in spatially separated material structures is disclosed. An electric field is applied to the separate material structure and the field is modulated spatially according to a protocol. The protocol represents a predetermined pattern of electrically conducting and/or semiconducting structures that are generated in the material structure in response to the field. The matrix composed by the material structures includes structures of this kind in three dimensions. A method for global erasing is also disclosed, wherein an electric field is applied to the matrix until the materials in the matrix, in their entirety, arrive in a non-conducting state in response to the field.

Abstract: In a method for optical data storage, a write/read device is employed with a first optical lens system consisting of an array of lenslets which are associated with one or more areas on a data-carrying medium which forms part of the optical data memory. During writing/reading of data in the data-carrying medium the optical data medium is positioned on one or more reference surfaces. When localizing or reading data which are stored in an optical data memory in this fashion, the data-carrying medium is brought in register with the first optical lens system in the write/read device, whereupon light from the write/read device passes through a set of angular coordinates, the optical response from the data-carrying medium being detected simultaneously and in parallel by means of the write/read device.

Abstract: Electrically conducting and/or semiconducting structures are generated in three dimensions in a composite matrix including two or more materials provided in spatially separate and homogenous material structures. Materials undergo specific physical and/or chemical changes causing transition from electrically non-conducing to electrically conducting and semiconducting state. The material structures are radiated with a given intensity or frequency characteristic adapted to the specific response of the material. Spatially modulating the radiation according to a protocol representing a pattern of electrically conducing and semiconducting structures in the relevant material structures generates the two dimensional electrically conducting and semiconducting structures in the material structure. The composite matrix is provided with electrically conducting and semiconducting structures in three dimensions. Spectral ranges of the radiation include gamma, x-ray, ultraviolet, visible light, inferred, and microwave.

Abstract: In a method of driving a passive matrix display or memory array of cells comprising an electrically polarizable material exhibiting hysteresis, in particular a ferroelectric material, wherein the polarization state of individual cells can be switched by application of electric potentials or voltages to word and bit lines in the matrix or array, a potential on selected word and bit lines is controlled to approach or coincide with one of n predefined potential levels and the potentials on all word and bit lines are controlled in time according to a protocol such that word lines are sequentially latched to potentials selected among nWORD potentials, while the bit lines are either latched sequentially to potentials selected among nBIT potentials, or during a certain period of a timing sequence given by the protocol connected to circuitry for detecting charges flowing between a bit line or bit lines and cells connecting thereto.

Abstract: A read-only memory is made electrically addressable over a passive conductor matrix, wherein the volume between intersection of two conductors (2; 4) in the matrix defines a memory cell (5). Data are stored as impedance values in the memory cells. The memory cells (5) comprise either an isolating material (6) which provides high impedance or one or more inorganic or organic semiconductors (9), preferably with an anisotropic conducting property. The semiconductor material (9) forms a diode junction at the interface to a metallic conductor (2; 4) in the matrix. By suitable arrangement of respectively the isolating material (6) and semiconductor material (9) in the memory cells these may be given a determined impedance value which may be read electrically and corresponds to logical values in a binary or multi-valued code. One or more read-only memories (ROM) may be provided on a semiconductor substrate (1) which also comprises driver and control circuits (13), to accomplish a read-only memory device.

Abstract: In a multilayer logic device or processor device with a plurality of individually matrix-addressable stacked thin layers of an active material, the active material in each layer is provided between a first electrode set and a second electrode set wherein the electrodes in the first set realize the columns and the electrodes in the second set the rows in an orthogonal array. The intersections between the electrodes in the array define logic cells in the layer of active material, and the stacked layers of active material are provided on a common supporting substrate. A separation layer with determined electrical or thermal properties is provided between each layer of active material.

Abstract: In a ferroelectric data processing device for processing and/or storage of data with passive or electrical addressing a data-carrying medium is used in the form of a thin film (1) of ferroelectric material which by an applied electric field is polarized to determined polarization states or switched between these and is provided as a continuous layer in or adjacent to electrode structures in the form of a matrix. A logic element (4) is formed at the intersection between an x electrode (2) and a y electrode (3) of the electrode matrix. The logic element (4) is addressed by applying to the electrodes (2, 3) a voltage greater than the coercivity field of the ferroelectric material.

Abstract: In a method for performing read and write operations in a passive matrix-addressed memory array of memory cells comprising an electrically polarizable material exhibiting polarization remanence, in particular an electret or ferroelectric material, wherein a logical value stored in a memory cell is represented by an actual polarization state in the memory cell, a degree of polarization in the polarizable material is limited during each read and write cycle to a value defined by a circuit device controlling the read and write operations, with said value ranging from zero to an upper limit corresponding to saturation of the polarization and consistent with predetermined criterta for a reliable detection of a logic state of a memory cell.

Abstract: In a multilayer logic device or processor device with a plurality of individually matrix-addressable stacked thin layers of an active material, the active material in each layer is provided between a first electrode set and a second electrode set wherein the electrodes in the first set realize the columns and the electrodes in the second set the rows in an orthogonal array. The intersections between the electrodes in the array define logic cells in the layer of active material, and the stacked layers of active material are provided on a common supporting substrate. A separation layer with determined electrical or thermal properties is provided between each layer of active material.

Abstract: A read-only memory is made electrically addressable over a passive conductor matrix, wherein at least a portion of the volume between intersection of two conductors (2;4) in the matrix defines a memory cell (5) in the read-only memory. Data are stored as impedance values in the memory cells. The memory cells (5) comprise either an isolating material (6) which provides high impedance or one or more inorganic or organic semiconductors (9), preferably with an anisotropic conducting property. The semiconductor material (9) forms a diode junction at the interface to a metallic conductor (2;4) in the matrix. By suitable arrangement of respectively the isolating material (6) and semiconductor material (9) in the memory cells these may be given a determined impedance value which may be read electrically and corresponds to logical values in a binary or multi-valued code.

Abstract: In a multistable optical logic element with a light-sensitive organic material (1) which undergoes a photocycle with several physical states by irradiation with light, and wherein a physical state is assigned a logical value which can be changed by addressing the element optically, the element initially before the addressing is in a metastable state generated in advance. A multistable optical logic element has been made proximity-addressable by providing at least a color light source (2) for optical addressing and at least one color-sensitive optical detector (5) adjacent to the light-sensitive material. In a method for preparing of the light-sensitive material (1) a desired initial metastable state is generated in the photocycle and assigned a determined logical value for the element.