Patents by Inventor Hans-Joachim Barth

Hans-Joachim Barth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Three-Dimensional Multichip Module
    Publication number: 20120313263
    Abstract: A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips.
    Type: Application
    Filed: August 16, 2012
    Publication date: December 13, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Hans-Joachim Barth
  • Semiconductor structure and method for making same
    Patent number: 8330274
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Gottfried Beer, Joern Plagmann, Jens Pohl, Werner Robl, Rainer Steiner, Mathias Vaupel
  • On-Chip RF Shields with Backside Redistribution Lines
    Publication number: 20120258594
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, a method of fabricating the system on chip includes forming a through substrate opening from a back surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry. The method further includes forming patterns for redistribution lines on a photo resist layer, the photo resist layer disposed under the back surface, and filling the through substrate opening and the patterns for redistribution lines with a conductive material.
    Type: Application
    Filed: April 11, 2011
    Publication date: October 11, 2012
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Heinrich Koerner
  • Cooling structures and methods
    Patent number: 8269341
    Abstract: Cooling structures and methods, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a cooling structure for a semiconductor device includes at least one channel defined between a first workpiece and a second workpiece. The second workpiece is bonded to the first workpiece. The at least one channel is adapted to retain a fluid.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: September 18, 2012
    Assignee: Infineon Technologies AG
    Inventor: Hans-Joachim Barth
  • Three-dimensional multichip module
    Patent number: 8247910
    Abstract: A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: August 21, 2012
    Assignee: Infineon Technologies AG
    Inventor: Hans-Joachim Barth
  • On-Chip RF Shields with Front Side Redistribution Lines
    Publication number: 20120208320
    Abstract: A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines.
    Type: Application
    Filed: April 26, 2012
    Publication date: August 16, 2012
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Hans-Joachim Barth, Thorsten Meyer, Markus Brunnbauer, Jenei Snezana
  • On-chip RF shields with front side redistribution lines
    Patent number: 8178953
    Abstract: A system on chip comprising a RF shield is disclosed. In one embodiment, the system on chip includes a RF component disposed on a chip, first redistribution lines disposed above the system on chip, the first redistribution lines coupled to I/O connection nodes. The system on chip further includes second redistribution lines disposed above the RF component, the second redistribution lines coupled to ground potential nodes. The second redistribution lines include a first set of parallel metal lines coupled together by a second set of parallel metal lines.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 15, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Thorsten Meyer, Markus Brunnbauer, Snezana Jenei
  • On-chip RF shields with through substrate conductors
    Patent number: 8169059
    Abstract: Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, the system on a chip includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary. The system on chip further includes through substrate conductors disposed in the substrate, the through substrate conductors coupled to a ground potential node, the through substrate conductors disposed around the RF component forming a fence around the RF circuit.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 1, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Jens Pohl, Gottfried Beer, Oliver Nagy
  • Semiconductor Devices and Methods of Manufacture Thereof
    Publication number: 20120099243
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.
    Type: Application
    Filed: January 6, 2012
    Publication date: April 26, 2012
    Applicant: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Erwin Ruderer, Alexander Von Glasow, Philipp Riess, Erdem Kaltalioglu, Peter Baumgartner, Thomas Benetik, Helmut Horst Tews
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME
    Publication number: 20120080791
    Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Inventors: Hans-Joachim BARTH, Gottfried BEER, Joern PLAGMANN, Jens POHL, Werner ROBL, Rainer STEINER, Mathias VAUPEL
  • Semiconductor structure and method for making same
    Patent number: 8148257
    Abstract: One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: April 3, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Gottfried Beer, Joern Plagmann, Jens Pohl, Werner Robl, Rainer Steiner, Mathias Vaupel
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME
    Publication number: 20120074574
    Abstract: One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Inventors: Hans-Joachim BARTH, Gottfried BEER, Joern PLAGMANN, Jens POHL, Werner ROBL, Rainer STEINER, Mathias VAUPEL
  • Semiconductor devices and methods of manufacture thereof
    Patent number: 8138539
    Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: March 20, 2012
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Erwin Ruderer, Alexander Von Glasow, Philipp Riess, Erdem Kaltalioglu, Peter Baumgartner, Thomas Benetik, Helmut Horst Tews
  • On-chip radio frequency shield with interconnect metallization
    Patent number: 8063469
    Abstract: Structure and method for fabricating a system on chip with an on-chip RF shield including interconnect metallization is described. In one embodiment, the system on chip includes an RF circuitry disposed on a first portion of a top surface of a substrate, and a semiconductor circuitry disposed on a second portion of the top surface of the substrate. An interconnect RF barrier is disposed between the RF circuitry and the semiconductor circuitry, the interconnect RF barrier coupled to a ground potential node.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: November 22, 2011
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Heinrich Koerner, Thorsten Meyer, Markus Brunnbauer
  • Three-Dimensional Multichip Module
    Publication number: 20110233775
    Abstract: A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips.
    Type: Application
    Filed: June 10, 2011
    Publication date: September 29, 2011
    Inventor: Hans-Joachim Barth
  • System on a Chip with On-Chip RF Shield
    Publication number: 20110201175
    Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
    Type: Application
    Filed: March 1, 2011
    Publication date: August 18, 2011
    Inventors: Hans-Joachim Barth, Andre Hanke, Snezana Jenei, Oliver Nagy, Jiro Morinaga, Bernd Adler, Heinrich Koerner
  • Three-dimensional multichip module
    Patent number: 7986033
    Abstract: A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: July 26, 2011
    Assignee: Infineon Technologies AG
    Inventor: Hans-Joachim Barth
  • Semiconductor device with inductor
    Patent number: 7986023
    Abstract: One or more embodiments are directed to a semiconductor structure, comprising: a support; a semiconductor chip at least partially embedded within the support; and an inductor electrically coupled to the chip, at least a portion of the inductor overlying the support outside the lateral boundary of the chip.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: July 26, 2011
    Assignee: Infineon Technologies AG
    Inventors: Helmut Tews, Hans-Gerd Jetten, Hans-Joachim Barth
  • System on a chip with on-chip RF shield
    Patent number: 7948064
    Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 24, 2011
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Andre Hanke, Snezana Jenei, Oliver Nagy, Jiro Morinaga, Bernd Adler, Heinrich Koerner
  • DEVICE FABRICATED USING AN ELECTROPLATING PROCESS
    Publication number: 20110101532
    Abstract: A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.
    Type: Application
    Filed: November 3, 2009
    Publication date: May 5, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Jens Pohl, Hans-Joachim Barth, Gottfried Beer, Rainer Steiner, Werner Robl, Mathias Vaupel