Abstract: The invention concerns an array and a method for dosing a hormone regulating the blood glucose, especially insulin, of a diabetic patient.

Abstract: The invention concerns an array and a method for dosing a hormone regulating the blood glucose, especially insulin, of a diabetic patient (10). In order to improve the administration of the hormone, the invention provides the following characteristic combination: a) a measuring device (16) to detect measured values correlatable with blood sugar; b) a controlling means (12) comprising a controller (44) and a hormone dosing device (46) for supplying a hormone dosage; c) a pilot control device (14) acting on the hormone fine dosage controlling means (12) for performing a coarse pre-control in accordance with at least one influence variable that influences blood glucose.

Abstract: The invention concerns an array and a method for dosing a hormone regulating the blood glucose, especially insulin of a diabetic patient (10). In order to improve the administration of the hormone, the invention provides the following characteristic combination: a) a measuring device (16) to detect measured values correlatable with blood sugar; b) a controlling means (12) comprising a controller (44) and a hormone dosing device (46) for supplying a hormone dosage; c) a pilot control device (14) acting on the hormone fine dosage controlling means (12) for performing a coarse pre-control in accordance with at least one influence variable that influences blood glucose.

Abstract: The invention concerns an arrangement for determining the concentration of glucose in a tissue fluid. In the microdialysis technology used for this purpose, perfusate-containing glucose is transported in intermittent delivery pulses through a microdialysis probe inserted into the tissue fluid and dialysate obtained in this process is passed to a measuring cell to record the glucose content. In order to achieve an exact determination of glucose even with a reduced dialysis period, it is proposed that the starting content of glucose in the perfusate is adapted to the glucose content of the tissue fluid by means of a control device in accordance with a command variable derived from the measurement signals of the measuring cell. When the control deviation is negligible the momentary starting content of glucose in the perfusate can be determined as a measure for the glucose content of the tissue fluid.

Abstract: The invention concerns a method and an arrangement for determining the concentration of glucose in a body fluid. In the microdialysis technology used for this purpose, perfusate containing glucose is transported in intermittent delivery pulses through a microdialysis probe (10) inserted into the body fluid and dialysate obtained in this process is passed to a measuring cell (16) to record the glucose content. In order to achieve an exact determination of glucose even with a reduced dialysis period, it is proposed that the starting content of glucose in the perfusate is adapted to the glucose content of the body fluid by means of a control device (18, 20) in accordance with a command variable derived from the measurement signals of the measuring cell (16). When the control deviation is negligible the momentary starting content of glucose in the perfusate can be determined as a measure for the glucose content of the body fluid.

Abstract: The invention concerns an arrangement for determining the concentration of glucose in a tissue fluid. In the microdialysis technology used for this purpose, perfusate-containing glucose is transported in intermittent delivery pulses through a microdialysis probe inserted into the tissue fluid and dialysate obtained in this process is passed to a measuring cell to record the glucose content. In order to achieve an exact determination of glucose even with a reduced dialysis period, it is proposed that the starting content of glucose in the perfusate is adapted to the glucose content of the tissue fluid by means of a control device in accordance with a command variable derived from the measurement signals of the measuring cell. When the control deviation is negligible the momentary starting content of glucose in the perfusate can be determined as a measure for the glucose content of the tissue fluid.

Abstract: The invention concerns an array and a method for dosing a hormone regulating the blood glucose, especially insulin of a diabetic patient (10). In order to improve the administration of the hormone, the invention provides the following characteristic combination: a) a measuring device (16) to detect measured values correlatable with blood sugar; b) a controlling means (12) comprising a controller (44) and a hormone dosing device (46) for supplying a hormone dosage; c) a pilot control device (14) acting on the hormone fine dosage controlling means (12) for performing a coarse pre-control in accordance with at least one influence variable that influences blood glucose.

Abstract: A digital neural network has a plurality of neurons (NR) completely meshed with one another, each of which comprises an evaluation stage having a plurality of evaluators (B) that is equal in number to the plurality of neurons (NR) and each of which comprises a decision stage having a decision unit (E). An adjustment information (INF.sub.E) that effects a defined pre-adjustment of the decision unit (E) can be supplied to every decision unit (E) by a pre-processing means via an information input. A weighting information (INF.sub.G) can be supplied to every evaluator (B) by a pre-processing means via an individual information input. An output information (INF.sub.A) can be output by every decision unit (E) to a post-processing means via a respective individual information output. The information outputs of the decision units (E) are each connected to an individual processing input of all evaluators (B) allocated to the appertaining decision unit (E).

Abstract: A static memory is constructed in a plurality of hierarchy levels. Beneficial realization possibilities are set forth with respect to the surface utilization for the drive and read-out circuits in the second hierarchy level which are especially critical. Memory cells that supply a strong cell signal are advantageously utilized so that a low expense is needed in the read circuit. By displacing periphery circuits into higher hierarchy levels, a short access time and a reduced surface requirement arise.

Abstract: Memory cells are disclosed that avoid the utilization of analog circuits in the memory peripheral circuits when they are utilized in static memory modules and that intended to enhance the disturbed reliability when confronted by technology modifications and parameter fluctuations. Write-in thereby occurs from a write data line via a write selection transistor and read-out occurs via a read selection transistor onto a read data line. A second inverter formed of two field effect transistors serves as a feedback element in order to statically maintain the cell information. Due to an implemented asymmetry in the dimensioning between the first and second inverters, the memory cell is significantly less susceptible to information loss upon read-out when compared to a heretofore known memory cell. A precharging of the read data line is not required with these memory cells.

Abstract: A differential amplifier having externally controllable power consumption. The differential amplifier has an external circuit stage for signal-dependent setting of the power consumption. The circuit stage is composed of two field effect transistors connected parallel to one another that are arranged in series with a resistor of the output side via which the current source of the differential amplifier is set. The field effect transistors are driven by a level-converting circuit proceeding from the amplifier input, this level-converting circuit being equipped with a control circuit. The control circuit defines the operating points of the field effect transistors with and without applied input signal and thus controls the signal-dependent boosting of the amplifier current.

Abstract: A differential amplifier having externally controllable power consumption. Differential amplifiers have a "static-bias" stage for setting the quiescent currents that flow in parallel circuit branches. Two field effect transistors that are connected parallel to one another are in series with an output resistor of this stage, these field effect transistors being driven via a level-converting circuit given the appearance of an input signal to be amplified, such that a voltage boost occurs at the output resistor. This voltage boost leads to a current boost in the differential amplifier. Good driver properties, a distortion-free signal transmission and a low dissipated power are provided by this external control of the two field effect transistors that results from the amplifier inputs.

Abstract: The differential amplifier has two n-channel or p-channel field effect transistors serving as controllable current sources which supply auxiliary currents upon appearance of an input signal which amplify the quiescent current. The inputs of the differential amplifier are connected to the gate terminals of the n-channel or p-channel field effect transistors via a level-converting circuit for converting the d.c. component of the input signal superimposed on a gate bias voltage to a lower or, respectively, higher output level. As a result of the control of the current sources proceeding from the amplifier input good driver qualities, a distortion-free signal transmission and a lower dissipation power are guaranteed.

Abstract: An integrated circuit in complementary circuit technology comprising two field effect transistors (T1, T2) of different channel types with the first one (T2) mounted in a doped semiconductor body (1) having a first conductivity type and the other FET (T1) mounted in a semiconductor zone 2 of a second conductivity type which is arranged in said body. The object is to provide a protection against thermal overloads which can appear due to "latch up" influences when overvoltages at the one connecting region of the field effect transistor (T1) mounted in the semiconductor zone occur.

Abstract: A transversal filter has an analog shift register exhibiting a series input and a plurality of parallel outputs which are connected to a summing and/or subtracting circuit. A simple realization of signal weighting circuits assigned to the stages of the shift register is achieved in that n signal weighting devices assigned to a group of n stages are disposed in a signal path which extends from the input of the first stage of the group over all stages thereof and in that the signal weighting devices of the n stages respectively weight according to filter coefficients b.sub.1 -b.sub.n which occur in the system functionH(z)=b.sub.0 .multidot.(1+b.sub.1 .multidot.z(1+b.sub.2 .multidot.z(. . . (1+b.sub.n .multidot.z))))determining the filtered signal, where z represents the delay time per stage for each signal value. The transversal filter of the invention is useful in analog filters of communications technology.

Abstract: A transversal filter with an analog shift register has a plurality of parallel inputs and a serial output at which a filtered signal appears. An object is to provide as simple as possible a realization of the n signal evaluators allocated to the n stages of the shift register. This is achieved by providing the n signal evaluators in a signal path proceeding from the input of the first stage over all n stages, and to evaluate according to evaluation factors b.sub.n through b.sub.1 which occur in the system functionH(z)=b.sub.o .multidot.(1+b.sub.1 z(1+b.sub.2 .multidot.z( . . . 1+b.sub.n .multidot.z)))describing the filtered signal, where z is the delay which the signal values respectively experience when traversing a stage of the shift register. The filter is employed as an analog filter in communication technology.

Abstract: A function check of a programmable logic array is performed in which input lines, product term lines and ground lines are combined into an AND plane and output lines, product term lines and ground lines are combined into an OR plane. The aim is a simple method of function check which permits any potentially-existing fault to be detected. The check is achieved by generating, with a test data generator, bit patterns and applying the same to the input lines, and, through the use of a shift register, successively sensitizing the product term lines either individually or in groups, i.e. disconnecting the same from ground potential. The bit patterns occurring at the output lines are supplied to a test data evaluator. The area of use is in logic circuitry of data processing technology.

Abstract: A two-dimensional image sensor integrated on a semiconductor substrate has a plurality of sensor elements disposed in rows and columns. The sensors in each row and column are individually selected in succession via parallel outputs of a vertical shift register for readout of the sensor elements. Regulation of the integration time during which charge carriers collect in the sensor elements due to incident light is achieved by selecting the sensor elements in each even-numbered row for readout a further number of times after an initial readout of the charges optically generated therein, and within the time span during which transfer of the charges from the sensor elements of the next odd-numbered rows to the column lines takes place. The further selections eliminate charges formed in the interim in a particular row.

Abstract: A circuit for sensor controlled distance measurement is disclosed having two linear image sensors which are positioned to receive corresponding lines of two images derived from an object. The sensor signals are subjected to correlation measurements from which the distance of the object is determined. In the case of circuits of this sort, one endeavors to attain as exact and unfalsified a distance measurement as possible. For this purpose, the sensor signals are digitalized in evaluators, then read via transfer transistors into shift registers which undertake relative position displacements of the sensor signals in a longitudinal direction of the image sensors between individual signal cycles, and are subject to a correlation measurement. The circuit distinguishes itself in that the digital evaluation proceeds completely independently of parameters of the shift register and is thus carried out very precisely. Applications include photographic and electronic cameras.

Abstract: A circuit for sensor-controlled telemetry has two linear image sensors each having a number of opto-electronic sensor elements on which are projected sections of corresponding lines of two separately-obtained images from an object whose range is to be determined and has a single-input evaluator post connected to each sensor element through switching transistors, which evaluators are switchable between two logic states dependent upon whether a voltage generated by accumulated charge in a sensor element is above or below a reference potential. The digitalized signals from each evaluator are serially transmitted through respective associated shift registers to a logic circuit which compares the contents of stages of shift registers for each image sensor for determining coincidence of the digital signals.