Abstract: In the fabrication of an integrated circuit, a shallow trench for isolation of a vertical bipolar transistor comprised in the circuit is fabricated by providing a semiconductor substrate of a first doping type. A buried collector region of a second doping type for the bipolar transistor is formed in the substrate. A silicon layer is epitaxially grown on top of the substrate. An active region of the second doping type for the bipolar transistor is formed in the epitaxially grown silicon layer, the active region being located above the buried collector region. A first trench is formed in the epitaxially grown silicon layer and the silicon substrate, the first trench surrounding, in a horizontal plane, the active region and extending vertically a distance into the substrate. An electrically insulating material is formed in the first trench.

Abstract: A method for producing vertical bipolar transistors having different voltage breakdown and high-frequency performance characteristics on a single die comprises forming, for each of the vertical bipolar transistors, a buried collector region, and base and emitter regions above the buried collector region. The lateral extensions and locations of the base and emitter regions and of the buried collector region are, for each of the vertical bipolar transistors, selected to create an overlap between the base and emitter regions, and the buried collector region, as seen from above, wherein at least some of the overlaps are selected to be different.

Abstract: A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n+-type region; forming field isolation areas around the n-type region; forming a PMOS gate region on the n-type region; forming a diffused n+-type contact from the upper surface of the substrate to the buried n+-type region; the contact being separated from the n-type region; forming a p-type polysilicon source on the n-type region; forming a p-type source in the n-type region; forming a p-type drain in the n-type region; and connecting the PMOS transistor structure to operate as a PNP transistor, wherein the source is connected to the gate and constitutes an emitter of the PNP transistor; the drain constitutes a collector of the PNP transistor; and the n-type region constitutes a base of the PNP transistor.

Abstract: A monolithically integrated circuit comprises a thin film resistor (8) with low resistance and low temperature coefficient; a high frequency lateral power transistor device (9) including gate (17), source (16) and drain (15) regions, and a Faraday shield layer region (22; 22?) above the gate region; and at least a first metallization layer (28) there above for electrical connection of the gate (17), source (16) and drain (15) regions through via holes filled with conductive material (29c–d). The thin film resistor (8) and the Faraday shield layer region (22; 22?) are made in the same conductive layer, which is arranged below the first metallization layer (28).

Abstract: A method in the fabrication of an integrated bipolar circuit for forming a p/n-junction varactor is disclosed. The method featuring the steps of providing a p-doped substrate (10; 10, 41); forming a buried n+-doped region (31) in the substrate; forming in the substrate an n-doped region (41) above the buried n+-doped region (31); forming field isolation (81) around the n-doped region (41); multiple ion implanting the n-doped region (41); forming a p+-doped region (151) on the n-doped region (41); forming an n+-doped contact region to the buried n+-doped region (31), the contact region being separated from the n-doped region (41); and heat treating the hereby obtained structure to set the doping profiles of the doped regions. The multiple ion implantation of the n-doped region (41); the formation of the p+-doped region (151); and the heat treatment are performed to obtain a hyper-abrupt p+/n-junction within the n-doped region (41).

Abstract: A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition.

Abstract: A method in the fabrication of a silicon-germanium mesa transistor in a semiconductor process flow comprises the steps of providing a p-type doped silicon bulk substrate (10) having an n+-type doped surface region (31) being a subcollector; depositing epitaxially thereon a silicon layer (41) comprising n-type dopant; depositing epitaxially thereon a silicon layer (174) comprising germanium and p-type dopant; forming in the epitaxial layers (41, 174) field isolation areas (81) around, in a horizontal plane, a portion of the epitaxial layers (41, 174) to simultaneously define an n-type doped collector region (41) on the subcollector (31); a p-type doped base region (174) thereon; and an n-type doped collector plug on the subcollector (31), but separated from the n-type doped collector region (41) and the p-type doped base region (174); and forming in the p-type doped base region (174) an n-type doped emitter region.

Abstract: In a bipolar double-poly transistor comprising a layer of base silicon (1?) on a silicon substrate (2?), a first layer of silicon dioxide (3?) on the base silicon layer (1?), an emitter window (4?) extending through the first layer (3?) of silicon dioxide and the base silicon layer (1?), a second layer (5?) of silicon dioxide in the emitter window (4?), silicon nitride spacers (6?) on the second layer (5?) of silicon dioxide in the emitter window (4?), and emitter silicon (9?) in the emitter window (4?), an isolating silicon nitride seal is provided to separate the base silicon (1?) from the emitter silicon (9?) to prevent short-circuiting between the base silicon (1?) and the emitter silicon (9?) in the transistor.

Abstract: A monolithically integrated circuit comprises a thin film resistor (8) with low resistance and low temperature coefficient; a high frequency lateral power transistor device (9) including gate (17), source (16) and drain (15) regions, and a Faraday shield layer region (22; 22?) above the gate region; and at least a first metallization layer (28) there above for electrical connection of the gate (17), source (16) and drain (15) regions through via holes filled with conductive material (29c-d). The thin film resistor (8) and the Faraday shield layer region (22; 22?) are made in the same conductive layer, which is arranged below the first metallization layer (28).

Abstract: A monolithically integrated high frequency lateral power transistor device comprises a semiconductor substrate (10; 40), a gate region (17; 41-43) including a gate semiconductor layer region (18, 42) on top of a gate insulation layer region (19, 41), source (16) and drain (15) regions, and a channel region arranged beneath the gate region, wherein the channel region interconnects the source and drain regions. An oxide region (21; 45) is provided on top of the gate region, wherein the oxide region overlaps the gate region and has a substantially planar upper surface (21a). A Faraday shield is provided as a conductive layer (22; 46) on top of the oxide region, wherein the conductive layer covers an edge (17a) of the gate region as seen from above, and leaves a portion (15a) of the drain region uncovered as seen from above.

Abstract: A monolithically integrated vertical DMOS transistor device comprises a semiconductor substrate (11), a gate including a gate semiconductor layer region (27) on top of a gate insulation layer region (25), a source (31), a drain including a buried drain region (13) and a drain contact (21), and a channel region (29) arranged beneath the gate region. The drain comprises a lightly doped, preferably retrograde doped, drain region (23) arranged between the gate and the buried drain region, and the source (31), the channel region (29) and the lightly doped drain region (23) are arranged in a doped well region (17), wherein the lightly doped drain region has a higher doping level than the well region to thereby enhance the high frequency properties of the vertical DMOS transistor device.

Abstract: A method in the fabrication of an integrated bipolar circuit comprises the steps of: providing a p-type substrate; forming in the substrate a buried n+-type region and an n-type region above the buried n+-type region; forming field isolation areas around the n-type region; forming a PMOS gate region on the n-type region; forming a diffused n+-type contact from the upper surface of the substrate to the buried n+-type region; the contact being separated from the n-type region; forming a p-type polysilicon source on the n-type region; forming a p-type source in the n-type region; forming a p-type drain in the n-type region; and connecting the PMOS transistor structure to operate as a PNP transistor, wherein the source is connected to the gate and constitutes an emitter of the PNP transistor; the drain constitutes a collector of the PNP transistor; and the n-type region constitutes a base of the PNP transistor.

Abstract: A method for selective etching in the manufacture of a semiconductor device comprises: forming a layer (6) of silicon-germanium on a substrate (1) of monocrystalline silicon or on a substrate at least comprising a surface layer of monocrystalline silicon, depositing at least a dielectric layer (7) on the silicon-germanium layer (6) and patterning the resultant structure (8), whereafter the dielectric layer (7) and the silicon-germanium layer (6) are etched away within a predetermined region (9). Preferably, the silicon-germanium layer (6) is amorphous, whereby the dielectric layer (7) is deposited on the amorphous silicon-germanium layer (6) in such a manner to prevent crystallization of the amorphous layer. After etching the structure may be heat-treated such that the amorphous layer crystallizes. The method is preferably applicable for etching an emitter window in the manufacture of a bipolar transistor having a self-registered base-emitter structure.

Abstract: An IC fabrication method comprises the steps of: providing a substrate (10, 41); forming an active region (41) for a bipolar transistor and an active region (41) for a MOS device in the substrate (10); forming isolation areas (81) around, in a horizontal plane, the active regions; forming a MOS gate region (111, 112) on the active region for the MOS device; forming a layer (141) of an insulating material on the MOS gate region and on the active region (31) for the transistor; and defining a base region in the active region for the transistor by producing an opening (143) in the insulating layer (141) such that the remaining portions of the insulating layer (141) partly cover the active region for the bipolar transistor. The insulating layer (141) remains on the MOS gate region to encapsulate and protect the MOS gate region during subsequent manufacturing steps.

Abstract: In a bipolar double-poly transistor comprising a layer of base silicon (1?) on a silicon substrate (2?), a first layer of silicon dioxide (3?) on the base silicon layer (1?), an emitter window (4?) extending through the first layer (3?) of silicon dioxide and the base silicon layer (1?), a second layer (5?) of silicon dioxide in the emitter window (4?), silicon nitride spacers (6?) on the second layer (5?) of silicon dioxide in the emitter window (4?), and emitter silicon (9?) in the emitter window (4?), an isolating silicon nitride seal is provided to separate the base silicon (1?) from the emitter silicon (9?) to prevent short-circuiting between the base silicon (1?) and the emitter silicon (9?) in the transistor.

Abstract: A method in the fabrication of an integrated bipolar circuit for forming a p/n-junction varactor is disclosed. The method featuring the steps of providing a p-doped substrate (10; 10, 41); forming a buried n+-doped region (31) in the substrate; forming in the substrate an n-doped region (41) above the buried n+-doped region (31); forming field isolation (81) around the n-doped region (41); multiple ion implanting the n-doped region (41); forming a p+-doped region (151) on the n-doped region (41); forming an n+-doped contact region to the buried n+-doped region (31), the contact region being separated from the n-doped region (41); and heat treating the hereby obtained structure to set the doping profiles of the doped regions. The multiple ion implantation of the n-doped region (41); the formation of the p+-doped region (151); and the heat treatment are performed to obtain a hyper-abrupt p+/n-junction within the n-doped region (41).

Abstract: A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition.

Abstract: A method in the fabrication of a silicon-germanium mesa transistor in a semiconductor process flow comprises the steps of providing a p-type doped silicon bulk substrate (10) having an n+-type doped surface region (31) being a subcollector; depositing epitaxially thereon a silicon layer (41) comprising n-type dopant; depositing epitaxially thereon a silicon layer (174) comprising germanium and p-type dopant; forming in the epitaxial layers (41, 174) field isolation areas (81) around, in a horizontal plane, a portion of the epitaxial layers (41, 174) to simultaneously define an n-type doped collector region (41) on the subcollector (31); a p-type doped base region (174) thereon; and an n-type doped collector plug on the subcollector (31), but separated from the n-type doped collector region (41) and the p-type doped base region (174); and forming in the p-type doped base region (174) an n-type doped emitter region.

Abstract: A method for selective etching in the manufacture of a semiconductor device comprises: forming a layer (6) of silicon-germanium on a substrate (1) of monocrystalline silicon or on a substrate at least comprising a surface layer of monocrystalline silicon, depositing at least a dielectric layer (7) on the silicon-germanium layer (6) and patterning the resultant structure (8), whereafter the dielectric layer (7) and the silicon-germanium layer (6) are etched away within a predetermined region (9). Preferably, the silicon-germanium layer (6) is amorphous, whereby the dielectric layer (7) is deposited on the amorphous silicon-germanium layer (6) in such a manner to prevent crystallization of the amorphous layer. After etching the structure may be heat-treated such that the amorphous layer crystallizes. The method is preferably applicable for etching an emitter window in the manufacture of a bipolar transistor having a self-registered base-emitter structure.

Abstract: A method for forming an electrical device structure in an integrated circuit comprises providing a substrate; forming a passivation layer thereon; forming a plurality of through holes in the passivation layer, the through holes; removing substrate material under the passivation layer by means of isotropic etching, thus forming at least a first cavity in the substrate beneath the plurality of through holes; forming a dielectric layer on top of the passivation layer to plug the through holes, thereby creating a membrane; and creating an electrical device, such as e.g. an inductor, above the membrane.