Patents by Inventor Hans-Oliver Joachim
Hans-Oliver Joachim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7102908Abstract: The present invention includes a ferro fuse cell comprising a ferroelectric storage capacitor electrically connected to a plate on one side and to a sense amplifier on the other side. A ferroelectric measurement capacitor is electrically connected between the ferroelectric storage capacitor and the sense amplifier.Type: GrantFiled: August 29, 2003Date of Patent: September 5, 2006Assignee: Infineon Technologies AGInventors: Roehr Thomas, Hans-Oliver Joachim, Nobert Rehm
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Patent number: 6999887Abstract: A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.Type: GrantFiled: August 6, 2003Date of Patent: February 14, 2006Assignee: Infineon Technologies AGInventors: Norbert Rehm, Hans-Oliver Joachim, Michael Jacob, Joerg Wohlfahrt
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Patent number: 6972983Abstract: Improved sensing of ferroelectric memory cells is disclosed. When a memory access is initiated, the bitlines are precharged to a negative voltage, for example, ?0.5 to ?1.0V. This increases the effective plateline pulse (VPLH) to VPLH+the magnitude of the negative voltage. This results in an increase in the difference between VHI and VL0 read signals, thereby increasing the sensing window.Type: GrantFiled: March 21, 2002Date of Patent: December 6, 2005Assignee: Infineon Technologies AktiengesellschaftInventors: Thomas Roehr, Hans-Oliver Joachim
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Patent number: 6906969Abstract: A redundancy unit includes first and second fuse blocks for programming the redundancy element. One fuse block has laser blowable fuses and the other electrical fuses. The redundancy unit can be programmed by either one of the fuse blocks, enabling the redundancy unit to able to be used for defects identified before packaging and as well as after.Type: GrantFiled: September 24, 2002Date of Patent: June 14, 2005Assignees: Infineon Technologies Aktiengesellschaft, Kabushiki Kaisha ToshibaInventors: Thomas Roehr, Hans-Oliver Joachim, Norbert Rehm, Tadashi Miyakawa
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Patent number: 6903959Abstract: A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on bitline true and bitline complement. The first reference voltage is used for sensing a cell on bitline true while the second reference voltage is used for sensing a cell on bitline complement.Type: GrantFiled: September 24, 2002Date of Patent: June 7, 2005Assignee: Infineon Technologies AktiengesellschaftInventors: Thomas Roehr, Hans-Oliver Joachim, Joerg Wohlfahrt, Norbert Rehm
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Patent number: 6885597Abstract: A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.Type: GrantFiled: September 10, 2002Date of Patent: April 26, 2005Assignees: Infineon Technologies Aktiengesellschaft, Kabushiki Kaisha ToshibaInventors: Thomas Roehr, Hans-Oliver Joachim, Michael Jacob, Joerg Wohlfahrt, Takashima Daisaburo
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Patent number: 6876590Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.Type: GrantFiled: November 20, 2002Date of Patent: April 5, 2005Assignee: Infineon Technologies, AGInventors: Hans-Oliver Joachim, Michael Jacob, Nobert Rehm
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Publication number: 20050063212Abstract: A semiconductor memory comprises a first capacitor for storing digital data connecting a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier connected to the first and reference bit-lines measures a differential read signal on the first and reference bit-lines. A toggle flip flop alternately changes the polarization of charge stored on the reference capacitors.Type: ApplicationFiled: September 18, 2003Publication date: March 24, 2005Inventors: Michael Jacob, Norbert Rehm, Hans-Oliver Joachim, Joerg Wohlfahrt
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Publication number: 20050063213Abstract: The present invention provides a semiconductor memory test mode configuration. A first capacitor stores digital data and connects a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier is connected to the first and reference bit-lines and measures a differential read signal on the first and reference bit-lines. A charge path reduces the differential read signal to determine the signal margin of the semiconductor memory.Type: ApplicationFiled: September 18, 2003Publication date: March 24, 2005Inventors: Michael Jacob, Thomas Roehr, Hans-Oliver Joachim
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Publication number: 20050050261Abstract: A data storage device comprises a controller, a FeRAM memory unit, and a flash memory unit having a much higher data storage capacity than the FeRAM memory unit. Initially, when data is received by the data storage device, the controller stores it in the FeRAM memory unit. This can be done very quickly, since FeRAM devices have a high write rate. Subsequently, the controller transfers the data to the flash memory unit. Thus, the data storage device combines the high storage rate ability of FeRAM devices and the high storage capacity of flash memory devices.Type: ApplicationFiled: August 27, 2003Publication date: March 3, 2005Inventors: Thomas Roehr, Michael Jacob, Nobert Rehm, Hans-Oliver Joachim
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Publication number: 20050047189Abstract: The present invention includes a ferro fuse cell comprising a ferroelectric storage capacitor electrically connected to a plate on one side and to a sense amplifier on the other side. A ferroelectric measurement capacitor is electrically connected between the ferroelectric storage capacitor and the sense amplifier.Type: ApplicationFiled: August 29, 2003Publication date: March 3, 2005Inventors: Roehr Thomas, Hans-Oliver Joachim, Norbert Rehm
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Patent number: 6856560Abstract: An improved redundancy scheme for chained memory architecture is disclosed. The redundancy scheme comprises including redundant cells as part of the memory chain. As such, a redundant cell is used to repair a defective cell within the chain. This eliminates the need in conventional chained architecture to replace the whole memory block when there is a defective cell.Type: GrantFiled: April 26, 2002Date of Patent: February 15, 2005Assignee: Infineon Technologies AktiengesellschaftInventors: Norbert Rehm, Hans-Oliver Joachim, Thomas Roehr, Joerg W. Wohlfahrt
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Publication number: 20050033541Abstract: A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.Type: ApplicationFiled: August 6, 2003Publication date: February 10, 2005Inventors: Norbert Rehm, Hans-Oliver Joachim, Michael Jacob, Joerg Wohlfahrt
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Patent number: 6826099Abstract: A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor which is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor which is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.Type: GrantFiled: November 20, 2002Date of Patent: November 30, 2004Assignee: Infineon Technologies AGInventors: Hans-Oliver Joachim, Thomas Roehr, Joerg Wohlfahrt
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Publication number: 20040208043Abstract: A FeRAM memory chip comprises an array 5 of non-volatile ferrocapacitor memory cells for storing data. Input pins receive data to be stored, and address data indicating where in the array of memory cells the data should be stored. The FeRAM memory chip further has a reset unit 7 for recognising an externally applied reset signal. The reset unit 7, upon recognition of the reset signal, initiates a reset operation in which at least a portion of the data stored in the memory cells is set to predetermined values.Type: ApplicationFiled: April 17, 2003Publication date: October 21, 2004Inventors: Joerg Wohlfahrt, Hans-Oliver Joachim
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Patent number: 6807084Abstract: A FeRAM memory chip comprises an array 5 of non-volatile ferrocapacitor memory cells for storing data. Input pins receive data to be stored, and address data indicating where in the array of memory cells the data should be stored. The FeRAM memory chip further has a reset unit 7 for recognizing an externally applied reset signal. The reset unit 7, upon recognition of the reset signal, initiates a reset operation in which at least a portion of the data stored in the memory cells is set to predetermined values.Type: GrantFiled: April 17, 2003Date of Patent: October 19, 2004Assignee: Infineon Technologies AGInventors: Joerg Wohlfahrt, Hans-Oliver Joachim
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Publication number: 20040095819Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Inventors: Hans-Oliver Joachim, Thomas Roehr, Joerg Wohlfahrt
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Publication number: 20040095821Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Inventors: Hans-Oliver Joachim, Michael Jacob, Nobert Rehm
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Publication number: 20040095799Abstract: The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data The capacitor connects a cell plate line to a first bit line through a first select transistor. The first select transistor is activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines.Type: ApplicationFiled: November 20, 2002Publication date: May 20, 2004Inventors: Michael Jacob, Thomas Roehr, Joerg Wohlfahrt, Hans-Oliver Joachim
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Publication number: 20040076031Abstract: Improved sensing of ferroelectric memory cells is disclosed. When a memory access is initiated, the bitlines are precharged to a negative voltage, for example, −0.5 to −1.0V. This increases the effective plateline pulse (VPLH) to VPLH+the magnitude of the negative voltage. This results in an increase in the difference between VHI and VL0 read signals, thereby increasing the sensing window.Type: ApplicationFiled: March 21, 2002Publication date: April 22, 2004Inventors: Thomas Roehr, Hans-Oliver Joachim