Patents by Inventor Hans-Oliver Joachim
Hans-Oliver Joachim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040057275Abstract: A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on bitline true and bitline complement. The first reference voltage is used for sensing a cell on bitline true while the second reference voltage is used for sensing a cell on bitline complement.Type: ApplicationFiled: September 24, 2002Publication date: March 25, 2004Inventors: Thomas Roehr, Hans-Oliver Joachim, Joerg Wohlfahrt, Norbert Rehm
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Publication number: 20040057293Abstract: A redundancy unit comprising first and second fuse blocks for programming the redundancy element is disclosed. One fuse block has laser blowable fuses and the other electrical fuses. The redundancy unit can be programmed by either one of the fuse blocks, enabling the redundancy unit to able to be used for defects identified before packaging and as well as after.Type: ApplicationFiled: September 24, 2002Publication date: March 25, 2004Inventors: Thomas Roehr, Hans-Oliver Joachim, Norbert Rehm, Tadashi Miyakawa
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Publication number: 20040057273Abstract: The present invention describes an information recorder which is integrated into an IC, such as ferroelectric RAM device. The recorder counts desired events, such as memory accesses or length of time powered up and stores such information in a latch. The information can be retrieved from the latch to assist in failure analysis and device characterization.Type: ApplicationFiled: September 24, 2002Publication date: March 25, 2004Inventors: Michael Klaus Jacob, Joerg Wilfried Wohlfahrt, Norbert Rehm, Hans-Oliver Joachim
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Patent number: 6707699Abstract: The present invention describes an information recorder which is integrated into an IC, such as ferroelectric RAM device. The recorder counts desired events, such as memory accesses or length of time powered up and stores such information in a latch. The information can be retrieved from the latch to assist in failure analysis and device characterization.Type: GrantFiled: September 24, 2002Date of Patent: March 16, 2004Assignee: Infineon Technologies AktiengesellschaftInventors: Michael Klaus Jacob, Joerg Wilfried Wohlfahrt, Norbert Rehm, Hans-Oliver Joachim
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Publication number: 20040047171Abstract: A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bitlines. During a read access, a selected memory cell produces a differential read signal on the bitlines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.Type: ApplicationFiled: September 10, 2002Publication date: March 11, 2004Inventors: Thomas Roehr, Hans-Oliver Joachim, Michael Jacob, Joerg Wohlfahrt, Takashima Daisaburo
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Patent number: 6687150Abstract: An improved reference voltage generation is described. In one embodiment, a memory block includes a plurality of memory cells interconnected by wordlines and bitlines. A plurality of reference cells are provided. A bitline includes a reference cell. The bitlines of the memory block are divided into groups or bitlines. The reference cells within a group are interconnected to average out the reference cell charge variation to improve the sensing window.Type: GrantFiled: September 4, 2002Date of Patent: February 3, 2004Assignees: Infineon Technologies Aktiengesellschaft, Kabushiki Kaisha ToshibaInventors: Hans-Oliver Joachim, Takashima Daisaburo
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Publication number: 20030202386Abstract: An improved redundancy scheme for chained memory architecture is disclosed. The redundancy scheme comprises including redundant cells as part of the memory chain. As such, a redundant cell is used to repair a defective cell within the chain. This eliminates the need in conventional chained architecture to replace the whole memory block when there is a defective cell.Type: ApplicationFiled: April 26, 2002Publication date: October 30, 2003Inventors: Norbert Rehm, Hans-Oliver Joachim, Thomas Roehr, Joerg W. Wohlfahrt
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Patent number: 6584009Abstract: A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first logic 1 voltage level. To prepare for a memory access, the non-selected wordlines are driven to a boosted voltage while the selected wordline is driven to ground. The first logic 1 voltage level is less than the boosted voltage. This reduces the stress on the gate oxide of the transistors, thus improving reliability of the memory IC.Type: GrantFiled: March 21, 2002Date of Patent: June 24, 2003Assignees: Infineon Technologies Aktiengesellschaft, Kabushiki Kaisha ToshibaInventors: Thomas Roehr, Hans-Oliver Joachim
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Patent number: 6323103Abstract: A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area.Type: GrantFiled: October 20, 1998Date of Patent: November 27, 2001Assignee: Siemens AktiengesellschaftInventors: Rajesh Rengarajan, Jochen Beintner, Ulrike Gruening, Hans-Oliver Joachim
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Patent number: 6323532Abstract: A semiconductor structure comprises first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators P-wells, wherein the first divots have a greater depth than the second divots.Type: GrantFiled: July 3, 2000Date of Patent: November 27, 2001Assignee: International Business Machines CorporationInventors: Hans-Oliver Joachim, Jack A. Mandelman, Rajesh Rengarajah
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Patent number: 6265742Abstract: A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.Type: GrantFiled: May 24, 1999Date of Patent: July 24, 2001Assignee: Siemens AktiengesellschaftInventors: Ulrike Gruening, Jochen Beintner, Hans-Oliver Joachim
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Patent number: 6236617Abstract: A negative wordline DRAM array having n groups of m wordlines, in which one group is driven by a group decoder circuit (having a voltage swing between ground and a circuit high voltage (2 v)) and one driver circuit in each group is exposed to a boosted wordline high voltage (2.8 v) greater than the circuit high voltage, in which the wordline driver circuits have an output stage comprising a standard nfet in series with a high threshold voltage pfet, so that, during activation, the unselected driver circuits exposed to the boosted wordline high voltage have a very low leakage through the pfet, while the selected driver circuit has a high but tolerable leakage (2 &mgr;A) because Vqs on the nfet is nearly at the nfet threshold.Type: GrantFiled: December 10, 1999Date of Patent: May 22, 2001Assignee: International Business Machines CorporationInventors: Louis L. Hsu, Hans-Oliver Joachim, Matthew R. Wordeman, Hing Wong
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Patent number: 6127215Abstract: A semiconductor structure comprises first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators adjacent P-wells, wherein the first divots have a greater depth than the second divots.Type: GrantFiled: October 29, 1998Date of Patent: October 3, 2000Assignees: International Business Machines Corp., Siemens Microelectronics, Inc.Inventors: Hans-Oliver Joachim, Jack A. Mandelman, Rajesh Rengarajan
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Patent number: 6093614Abstract: A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.Type: GrantFiled: March 4, 1998Date of Patent: July 25, 2000Assignee: Siemens AktiengesellschaftInventors: Ulrike Gruening, Jochen Beintner, Hans-Oliver Joachim
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Patent number: 5926703Abstract: It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6').Type: GrantFiled: January 21, 1997Date of Patent: July 20, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuo Yamaguchi, Hans-Oliver Joachim, Yasuo Inoue
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Patent number: 5641980Abstract: It is an object to obtain a semiconductor device with the LDD structure having both operational stability and high speed and a manufacturing method thereof. A high concentration region (11) with boron of about 1.times.10.sup.18 /cm.sup.3 introduced therein is formed extending from under a channel formation region (4) to under a drain region (6) and a source region (6') in a silicon substrate (1). The high concentration region (11) is formed in the surface of the silicon substrate (1) under the channel formation region (4), and is formed at a predetermined depth from the surface of the silicon substrate (1) under the drain region (6) and the source region (6'). A low concentration region (10) is formed in the surface of the silicon substrate (1) under the drain region (6) and the source region (6').Type: GrantFiled: November 14, 1995Date of Patent: June 24, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuo Yamaguchi, Hans-Oliver Joachim, Yasuo Inoue