Patents by Inventor Hans Reisinger

Hans Reisinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7402490
    Abstract: To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: July 22, 2008
    Assignee: Infineon Technologies AG
    Inventors: Thomas Mikolajick, Hans Reisinger, Josef Willer, Corvin Liaw
  • Patent number: 7049651
    Abstract: The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: May 23, 2006
    Assignee: Infineon Technologies AG
    Inventors: Thomas Mikolajick, Hans Reisinger, Josef Willer, Corvin Liaw
  • Publication number: 20060091448
    Abstract: To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.
    Type: Application
    Filed: October 19, 2005
    Publication date: May 4, 2006
    Inventors: Thomas Mikolajick, Hans Reisinger, Josef Willer, Corvin Liaw
  • Patent number: 6995416
    Abstract: The invention provides a memory device for storing electrical charge, which has, as memory elements, tube elements applied on an electrode layer and connect-connected thereto. The tube elements are provided with a dielectric coating, a filling material for filling the space between the tube elements being provided. A counter-electrode connected to the filling material is formed such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode. The tube elements advantageously comprise carbon nanotubes, as a result of which the capacitance of the capacitor on account of a drastic increase in the area of the capacitor electrode surface.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: February 7, 2006
    Assignee: Infineon Technologies AG
    Inventors: Hans Reisinger, Reinhard Stengl, Herbert Schäfer
  • Publication number: 20050104117
    Abstract: The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.
    Type: Application
    Filed: November 17, 2003
    Publication date: May 19, 2005
    Inventors: Thomas Mikolajick, Hans Reisinger, Josef Willer, Corvin Liaw
  • Patent number: 6887437
    Abstract: A reactor configuration contains a housing connected to a silicon wafer. The silicon wafer has pores extending from a first main area of the silicon wafer into an interior of the silicon wafer, preferably as far as a second main area of the silicon wafer. A catalyst layer at least partly covers the surface of the pores.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: May 3, 2005
    Assignee: Infineon Technologies AG
    Inventors: Volker Lehmann, Stefan Ottow, Reinhard Stengl, Hans Reisinger, Hermann Wendt
  • Publication number: 20040262637
    Abstract: The invention provides a memory device for storing electrical charge, which has, as memory elements, tube elements applied on an electrode layer and connect-connected thereto. The tube elements are provided with a dielectric coating, a filling material for filling the space between the tube elements being provided. A counter-electrode connected to the filling material is formed such that an electrical capacitor for storing electrical charge is formed between the electrode layer and the counter-electrode. The tube elements advantageously comprise carbon nanotubes, as a result of which the capacitance of the capacitor on account of a drastic increase in the area of the capacitor electrode surface.
    Type: Application
    Filed: May 26, 2004
    Publication date: December 30, 2004
    Applicant: Infineon Technologies AG
    Inventors: Hans Reisinger, Reinhard Stengl, Herbert Schafer
  • Patent number: 6710388
    Abstract: A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: March 23, 2004
    Assignee: Infineon Technologies AG
    Inventors: Thomas Peter Haneder, Hans Reisinger, Reinhard Stengl, Harald Bachhofer, Hermann Wendt, Wolfgang Hönlein
  • Patent number: 6627940
    Abstract: A memory-cell array includes a substrate forming parallel first and second trenches. A transistor's upper source/drain region adjoins two of the first and two of the second trenches, and lies above its lower source/drain region. A conductive structure in a first trench associated with the transistor adjoins the upper source/drain region at its first edge. An insulating structure in the associated first trench insulates the conductive structure from a second edge and from a bottom of the associated first trench. A word line, on which is a further insulating layer, is over the upper/source drain region and parallel to the associated first trench bulges into the second trenches. Insulating spaces adjoin the word line laterally. A contact on the conductive structure and in electrical communication with the upper source/drain region connects with a capacitor.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: September 30, 2003
    Assignee: Infineon Technologies AG
    Inventors: Dirk Schumann, Bernhard Sell, Hans Reisinger, Josef Willer
  • Patent number: 6614575
    Abstract: An optical structure includes a substrate having semiconductor material and a grating structure. The grating structure has the property of emitting at least one frequency band so that light having a frequency from that frequency band cannot propagate in the grating structure. The grating structure has a configuration of pores and a defective region. The pores are disposed outside the defective region in a periodic array, and the periodic array is disturbed in the defective region. A surface of the grating structure is provided with a conductive layer at least in the vicinity of the defective region. A method for producing the optical structure is also provided.
    Type: Grant
    Filed: August 10, 2000
    Date of Patent: September 2, 2003
    Assignee: Infineon Technologies AG
    Inventors: Ulrike Grüning, Volker Lehmann, Reinhard Stengl, Hermann Wendt, Hans Reisinger
  • Patent number: 6614066
    Abstract: A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: September 2, 2003
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Stengl, Hans Reisinger, Thomas Haneder, Harald Bachhofer
  • Publication number: 20030114018
    Abstract: The present invention provides a method for fabricating a semiconductor component having a substrate (1) and a dielectric layer (70) provided on or in the substrate (1), the dielectric layer (7) being deposited in alternating self-limiting monolayer form, in the form of at least two different precursors, by means of an ALD process. There is provision for conditioning of the surface of the substrate (1) prior to the deposition of a first monolayer of a first precursor with respect to a reactive ligand of the first precursor.
    Type: Application
    Filed: June 26, 2002
    Publication date: June 19, 2003
    Inventors: Martin Gutsche, Thomas Hecht, Stefan Jakschik, Matthias Leonhardt, Hans Reisinger, Uwe Schroeder, Kristin Schupke, Harald Seidl
  • Patent number: 6558770
    Abstract: A substrate made from silicon has a first region and a second region. Through pores are formed in the first region. Pores that do not traverse the substrate are provided in the second region. The production of the work piece is performed with the aid of electrochemical etching of the pores. The entire surface of the substrate is covered with a mask layer that is structured photolithographically on the rear of the substrate. The bottoms of the pores in the second region are etched clear, preferably using KOH.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: May 6, 2003
    Assignee: Infineon Technologies AG
    Inventors: Volker Lehmann, Hans Reisinger, Hermann Wendt, Reinhard Stengel, Gerrit Lange, Stefan Ottow
  • Patent number: 6552385
    Abstract: A DRAM capacitor is described that contains a BaSrTiO3 (BST) dielectric. The dielectric has a three-layer structure enabling the formation of a potential trough in which electrons can be permanently trapped.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: April 22, 2003
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Beitel, Martin Franosch, Thomas Peter Haneder, Gerrit Lange, Hans Reisinger, Herbert Schäfer, Stephan Schlamminger, Hermann Wendt
  • Patent number: 6548846
    Abstract: A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: April 15, 2003
    Assignee: Infineon Technologies AG
    Inventors: Hans Reisinger, Volker Lehmann, Reinhard Stengl, Hermann Wendt, Gerrit Lange, Harald Bachhofer, Martin Franosch, Herbert Schäfer
  • Patent number: 6534362
    Abstract: A method for fabricating a memory cell configuration, which includes the steps of etching isolation trenches into a semiconductor substrate and thereby forming webs between the isolation trenches and producing bit lines after channel regions have been produced. It furthermore includes performing an etching step which results in the isolation trenches penetrating more deeply into the semiconductor substrate.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: March 18, 2003
    Assignee: Infineon Technologies AG
    Inventor: Hans Reisinger
  • Patent number: 6518613
    Abstract: A MOS transistor of a memory cell and a bit line connected thereto are disposed on a first surface of a substrate. A capacitor of the memory cell is disposed on a second surface of the substrate, the second surface being opposite to the first surface. A contact is disposed in the substrate and connects the capacitor to the MOS transistor.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: February 11, 2003
    Assignee: Infineon Technologies AG
    Inventors: Josef Willer, Hans Reisinger, Till Schlosser, Reinhard Stengl
  • Patent number: 6469887
    Abstract: A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: October 22, 2002
    Assignee: Infineon Technologies AG
    Inventors: Harald Bachhofer, Thomas Haneder, Reinhard Stengl, Wolfgang Hönlein, Hans Reisinger
  • Patent number: 6468348
    Abstract: An open form is produced with a plurality of in each case two-dimensionally structured layers. The form is made of silicon which is etchable in dependence on its doping. A first silicon layer is first produced, and a portion of the first layer which belongs to the form to be produced, is marked by doping at least one zone of the first layer. Subsequently, at least one further silicon layer is applied, and a portion belonging to the form is also marked therein. Finally, every unmarked portion of the layers is removed by etching depending on the respective doping of each layer. The open form is, in particular, a photonic crystal.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: October 22, 2002
    Assignee: Infineon Technologies AG
    Inventors: Ulrike Grüning, Hermann Wendt, Volker Lehmann, Reinhard Stengl, Hans Reisinger
  • Publication number: 20020126543
    Abstract: A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.
    Type: Application
    Filed: December 11, 2000
    Publication date: September 12, 2002
    Inventors: Hans Reisinger, Volker Lehmann, Reinhard Stengl, Hermann Wendt, Gerrit Lange, Harald Bachhofer, Martin Franosch, Herbert Schafer