Abstract: A semiconductor structure for protecting integrated circuits from ESD pulses includes a semiconductor substrate of a first conductivity type and with a first dopant concentration. A well of a second conductivity type and with a second dopant concentration lies within the semiconductor substrate. Additionally, the semiconductor structure comprises a first area of a first conductivity type and with a third dopant concentration, wherein at least a first part of the area lies within the well. Further, there is a second area of a first conductivity type and with a fourth dopant concentration, the second area being fully within the well. A first protective zone of a second conductivity type and with a fifth dopant concentration lies in the well between the first area and the second area.

Abstract: A field effect transistor includes a substrate having a doping of a first conductivity type, a drain area in the substrate having a doping of a second conductivity type oppposite the first conductivity type, a source area in the substrate being laterally spaced from the drain area and having a doping of the second conductivity type, and a channel area in the substrate that is arranged between the source area and the drain area. In a portion of the substrate bordering the drain area, an area having a doping of the second conductivity type, which is connected to the drain area, is arranged such that in the portion alternating regions having the first conductivity type and having the second conductivity type are arranged.

Abstract: A semiconductor structure includes a substrate, a source area formed in the substrate and a drain area formed in the substrate and comprising a doping of a first conductivity type. The drain area includes a first drain portion with a first doping concentration and a second drain portion with a second doping concentration, wherein the first doping concentration is higher than the second doping concentration. In the second drain portion a first region is formed comprising a doping of a second conductivity type which is different to the first conductivity type. Further, a second region is formed in the substrate below the second drain portion comprising a doping of the first conductivity type. A channel area is provided in the substrate between the source area and the second drain portion.

Abstract: A high-frequency switching transistor comprises a substrate having a substrate dopant concentration and a barrier region bordering on the substrate, which has a first conductivity type, wherein a barrier region dopant concentration is higher than the substrate dopant concentration. Further, the high-frequency switching transistor comprises a source region embedded in the barrier region, which comprises a second conductivity type different to the first conductivity type, and has a source region dopant concentration, which is higher than the barrier region dopant concentration. Additionally, the high-frequency switching transistor comprises a drain region embedded in the barrier region and disposed offset from the source region, which comprises the second conductivity type and has a drain region dopant concentration, which is higher than the barrier region dopant concentration.

Abstract: In an inventive MOS transistor having a source region, a drain region and a channel region, which are formed in a semiconductor layer of an SOI substrate, which has a semiconductor substrate below the semiconductor layer and an isolation layer between semiconductor layer and semiconductor substrate, the drain or source region is electrically connected to a backside contact on a side of the semiconductor substrate facing away from the isolation layer by a via running through the semiconductor substrate. The central idea of the present invention is to obtain an easy contactability of an MOS transistor without limitations in the application spectrum, by leading a via either from the source or the drain region across both the isolation layer and the semiconductor substrate to a backside contact, to be electrically connected to the same, since thereby the requirements of the material properties of the semiconductor substrates, such as doping and conductivity, are unnecessary or reduced.

Abstract: A circuit is enabled to capacitively drive a memory cell (erasing, programming, and reading) via a capacitance. The capacitance is additionally present and isolates the antenna from the driver circuit of the memory cell. Charge accumulates on the antenna in the case of a FIB attack. The capacitance prevents the charge from flowing away, so that the voltage thus generated acts on the memory cell, which thus experiences a corresponding alteration of its charge state, which is detected. The capacitance can be implemented and realized in any conventional manner, such as any arbitrary capacitor structure of the circuit.

Abstract: A semiconductor structure comprises a substrate and a source region formed in the substrate. Further, a drain region is formed in the substrate. The drain region comprises a first drain portion with a first doping concentration and a second drain portion with a second doping concentration, which is lower than the first doping concentration. Between the source region and the second drain portion a channel region is defined. Further, a field plate is provided, which is disposed across the junction between the first drain portion and the second drain portion to reduce the gradient of the electrical field at the junction.

Abstract: A semiconductor structure for protecting integrated circuits from ESD pulses includes a semiconductor substrate of a first conductivity type and with a first dopant concentration. A well of a second conductivity type and with a second dopant concentration lies within the semiconductor substrate. Additionally, the semiconductor structure comprises a first area of a first conductivity type and with a third dopant concentration, wherein at least a first part of the area lies within the well. Further, there is a second area of a first conductivity type and with a fourth dopant concentration, the second area being fully within the well. A first protective zone of a second conductivity type and with a fifth dopant concentration lies in the well between the first area and the second area.

Abstract: A time recording device employs a floating gate cell, wherein an ON layer structure or an ONO layer structure is provided between floating gate and control gate. A charge injection unit is provided to inject charges into the floating gate electrode and into the nitride layer of the ON structure or the ONO structure by applying a voltage or voltage pulses to the control gate electrode, a center of concentration of the charges injected into the nitride layer being located at the interface between oxide layer and nitride layer of the layer sequence. The time recording device also includes a unit for recording a time which has elapsed since charge injection on the basis of changes in the transmission behavior of the channel region caused by a shift in the center of concentration of the charges in the nitride layer away from the interface.

Abstract: A Schottky diode has a Schottky junction formed by a thin metal layer and/or metal silicide layer at the top side of a doped well in a semiconductor body or substrate. In contrast to the fabrication of low-impedance contacts on CMOS wells, a metal, to be precise titanium in the preferred embodiment, is applied not to a highly doped contact region but to the lightly doped semiconductor material of the doped well, for example an HV well for the fabrication of high-voltage transistors.

Abstract: A semiconductor structure includes a substrate, a source area formed in the substrate and a drain area formed in the substrate and comprising a doping of a first conductivity type. The drain area includes a first drain portion with a first doping concentration and a second drain portion with a second doping concentration, wherein the first doping concentration is higher than the second doping concentration. In the second drain portion a first region is formed comprising a doping of a second conductivity type which is different to the first conductivity type. Further, a second region is formed in the substrate below the second drain portion comprising a doping of the first conductivity type. A channel area is provided in the substrate between the source area and the second drain portion.

Abstract: A semiconductor structure comprises a substrate and a source region formed in the substrate. Further, a drain region is formed in the substrate. The drain region comprises a first drain portion with a first doping concentration and a second drain portion with a second doping concentration, which is lower than the first doping concentration. Between the source region and the second drain portion a channel region is defined. Further, a field plate is provided, which is disposed across the junction between the first drain portion and the second drain portion to reduce the gradient of the electrical field at the junction.

Abstract: A semiconductor device has a substrate and an active area formed within the same includes a first non-planar metallization level which is formed on the substrate and is in contact with an active area. Further, a second planar metallization level is arranged above the substrate spaced apart from the first metallization level and is connected to the first metallization level via a through connection.

Abstract: A field effect transistor includes a substrate having a doping of a first conductivity type, a drain area in the substrate having a doping of a second conductivity type oppposite the first conductivity type, a source area in the substrate being laterally spaced from the drain area and having a doping of the second conductivity type, and a channel area in the substrate that is arranged between the source area and the drain area. In a portion of the substrate bordering the drain area, an area having a doping of the second conductivity type, which is connected to the drain area, is arranged such that in the portion alternating regions having the first conductivity type and having the second conductivity type are arranged.

Abstract: An apparatus for protecting an integrated circuit formed in a substrate and a method for protecting the integrated circuit against reverse engineering includes an active shield having a signal transmitter, a signal receiver, at least two conductor tracks running between the signal transmitter and the signal receiver, and a drive and evaluation device connected to the signal transmitter and to the signal receiver. The shield at least partially covers the integrated circuit. A covering composition applied on the substrate forms a mechanical protection of the integrated circuit. The shield has a switching apparatus. As a result, a capacitive measurement method can be carried out in a first switching state and damage to the shield can be detected in a second switching state.

Abstract: A circuit is enabled to capacitively drive a memory cell (erasing, programming, and reading) via a capacitance. The capacitance is additionally present and isolates the antenna from the driver circuit of the memory cell. Charge accumulates on the antenna in the case of a FIB attack. The capacitance prevents the charge from flowing away, so that the voltage thus generated acts on the memory cell, which thus experiences a corresponding alteration of its charge state, which is detected. The capacitance can be implemented and realized in any conventional manner, such as any arbitrary capacitor structure of the circuit.

Abstract: A time recording device employs a floating gate cell, wherein an ON layer structure or an ONO layer structure is provided between floating gate and control gate. A charge injection unit is provided to inject charges into the floating gate electrode and into the nitride layer of the ON structure or the ONO structure by applying a voltage or voltage pulses to the control gate electrode, a center of concentration of the charges injected into the nitride layer being located at the interface between oxide layer and nitride layer of the layer sequence. The time recording device also includes a unit for recording a time which has elapsed since charge injection on the basis of changes in the transmission behavior of the channel region caused by a shift in the center of concentration of the charges in the nitride layer away from the interface.

Abstract: A Schottky diode has a Schottky junction formed by a thin metal layer and/or metal silicide layer at the top side of a doped well in a semiconductor body or substrate. In contrast to the fabrication of low-impedance contacts on CMOS wells, a metal, to be precise titanium in the preferred embodiment, is applied not to a highly doped contact region but to the lightly doped semiconductor material of the doped well, for example an HV well for the fabrication of high-voltage transistors.

Abstract: An apparatus for protecting an integrated circuit formed in a substrate and a method for protecting the integrated circuit against reverse engineering includes an active shield having a signal transmitter, a signal receiver, at least two conductor tracks running between the signal transmitter and the signal receiver, and a drive and evaluation device connected to the signal transmitter and to the signal receiver. The shield at least partially covers the integrated circuit. A covering composition applied on the substrate forms a mechanical protection of the integrated circuit. The shield has a switching apparatus. As a result, a capacitive measurement method can be carried out in a first switching state and damage to the shield can be detected in a second switching state.