Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.

Abstract: A method includes forming a mask layer over a dielectric layer; patterning the mask layer to form a plurality of openings in the mask layer, the plurality of openings comprising a first opening and a second opening adjacent to the first opening, wherein a recessed region of the mask layer is located between the first opening and the second opening; forming a spacer layer over the patterned mask layer, wherein the spacer layer forms a spacer portion in the recessed region, the spacer portion spanning between the first opening and the second opening; etching the dielectric layer using the patterned mask layer and the spacer layer as an etch mask to form a plurality of conductive feature openings in the dielectric layer; forming a plurality of conductive features in the plurality of conductive feature openings.

Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.

Abstract: A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.

Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.

Abstract: The present application provides a medical image recognition method. The method includes obtaining a fundus image. A feature extraction model is invoked to extract features from the fundus image to obtain a fundus feature map. Once the fundus feature map is input into an attention mechanism model to obtain an attention-weighted feature map, a classification model is invoked to classify the attention-weighted feature map to obtain a target disease label of the fundus image. The present application also provides a method for training a medical image recognition model and an electronic device.

Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is formed in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.

Abstract: A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is formed in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.

Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.

Abstract: A method of manufacturing a semiconductor device includes forming an underlying structure in a first area and a second area over a substrate. A first layer is formed over the underlying structure. The first layer is removed from the second area while protecting the first layer in the first area. A second layer is formed over the first area and the second area, wherein the second layer has a smaller light transparency than the first layer. The second layer is removed from the first area, and first resist pattern is formed over the first layer in the first area and a second resist pattern over the second layer in the second area.

Abstract: In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.

Abstract: A first group of semiconductor fins are over a first region of a substrate, the substrate includes a first stepped profile between two of the first group of semiconductor fins, and the first stepped profile comprises a first lower step, two first upper steps, and two first step rises extending from opposite sides of the first lower step to the first upper steps. A second group of semiconductor fins are over a second region of the substrate, the substrate includes a second stepped profile between two of the second group of semiconductor fins, and the second stepped profile comprises a second lower step, two second upper steps, and two second step rises extending from opposite sides of the second lower step to the second upper steps, in which the second upper steps are wider than the first upper steps in the cross-sectional view.

Abstract: In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.

Abstract: A method of forming a memory structure includes the following steps. A CMOS circuitry is formed over a semiconductor substrate. A bit line array is formed to be electrically connected to the CMOS circuitry. A memory array is formed over the bit line array. The memory array is formed by forming a word line stack, and forming first and second sets of stacked memory cells. The word line stack is formed on the bit line array and has a first side surface and a second side surface. The first sets of stacked memory cells are formed along the first side surface. The second sets of stacked memory cells are formed along the second side surface, wherein the second sets of stacked memory cells are staggered from the first sets of stacked memory cells. A source line array is formed over the memory array and electrically connected to the CMOS circuitry.

Abstract: A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.

Abstract: A method of forming a memory structure includes the following steps. A CMOS circuitry is formed over a semiconductor substrate. A bit line array is formed to be electrically connected to the CMOS circuitry. A memory array is formed over the bit line array. The memory array is formed by forming a word line stack, and forming first and second sets of stacked memory cells. The word line stack is formed on the bit line array and has a first side surface and a second side surface. The first sets of stacked memory cells are formed along the first side surface. The second sets of stacked memory cells are formed along the second side surface, wherein the second sets of stacked memory cells are staggered from the first sets of stacked memory cells. A source line array is formed over the memory array and electrically connected to the CMOS circuitry.