Patents by Inventor Hanyi Ding

Hanyi Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10379191
    Abstract: The disclosure relates to an apparatus and a method for vector scattering parameter (s-parameter) measurements, and more particularly, to an apparatus and a method for providing a simple, low cost solution for tests requiring vector s-parameter measurements. The apparatus includes a source which provides an input signal, a divider which splits the input signal to a reference signal and a testing signal, a phase shifter which shifts the reference signal by a first phase and outputs a phase shifted signal, a device under test (DUT) which shifts the testing signal by a second phase and outputs a DUT shifted signal, a combiner which combines the phase shifted signal and the DUT shifted signal into a combined signal, and a detector which detects a product of the phase shifted signal and the DUT shifted signal.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: August 13, 2019
    Assignee: GLOBALGOUNDRIES INC.
    Inventors: Adem G. Aydin, Hanyi Ding
  • Patent number: 10256204
    Abstract: Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 9, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Glen E Richard, Stephen P Ayotte, Hanyi Ding
  • Publication number: 20180136304
    Abstract: The disclosure relates to an apparatus and a method for vector scattering parameter (s-parameter) measurements, and more particularly, to an apparatus and a method for providing a simple, low cost solution for tests requiring vector s-parameter measurements. The apparatus includes a source which provides an input signal, a divider which splits the input signal to a reference signal and a testing signal, a phase shifter which shifts the reference signal by a first phase and outputs a phase shifted signal, a device under test (DUT) which shifts the testing signal by a second phase and outputs a DUT shifted signal, a combiner which combines the phase shifted signal and the DUT shifted signal into a combined signal, and a detector which detects a product of the phase shifted signal and the DUT shifted signal.
    Type: Application
    Filed: January 11, 2018
    Publication date: May 17, 2018
    Inventors: Adem G. AYDIN, Hanyi DING
  • Publication number: 20180130733
    Abstract: Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.
    Type: Application
    Filed: November 8, 2016
    Publication date: May 10, 2018
    Inventors: Glen E. Richard, Stephen P. Ayotte, Hanyi Ding
  • Publication number: 20180102318
    Abstract: A compound resistor structure can use multiple electrically conductive pads connected by resistive elements to provide the equivalent resistance of a conventional resistor while spreading generated heat over a larger area. An array of pads and resistive elements can create larger resistances, metal connectors between rows of pads allowing current to flow from a first pad in a first row to a last pad in a last row via pads and resistive elements in each row. Fuses connecting pads in such an array can be included to allow tuning of resistance and/or other electrical properties.
    Type: Application
    Filed: October 12, 2016
    Publication date: April 12, 2018
    Inventors: Cathryn J. Christiansen, Hanyi Ding, Baozhen Li
  • Patent number: 9910124
    Abstract: The disclosure relates to an apparatus and a method for vector scattering parameter (s-parameter) measurements, and more particularly, to an apparatus and a method for providing a simple, low cost solution for tests requiring vector s-parameter measurements. The apparatus includes a source which provides an input signal, a divider which splits the input signal to a reference signal and a testing signal, a phase shifter which shifts the reference signal by a first phase and outputs a phase shifted signal, a device under test (DUT) which shifts the testing signal by a second phase and outputs a DUT shifted signal, a combiner which combines the phase shifted signal and the DUT shifted signal into a combined signal, and a detector which detects a product of the phase shifted signal and the DUT shifted signal.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: March 6, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Adem G. Aydin, Hanyi Ding
  • Patent number: 9865514
    Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hanyi Ding, J. Edwin Hostetter, Ping-Chuan Wang, Kimball M. Watson
  • Patent number: 9813264
    Abstract: Tunable phase shifters and methods for using the same include a signal line; one or more grounding lines; one or more crossing lines below the signal line in proximity to the signal line and substantially perpendicular to a longitudinal direction of the signal line, where the crossing lines conform to the shape of the signal line along at least three surfaces of the signal line and where the crossing lines have a tunable capacitance; and an inductance return line below the crossing lines substantially parallel to the longitudinal direction of the signal line, where the inductance return line provides a tunable inductance.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: November 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Alberto Valdes Garcia, Wayne H. Woods, Jr.
  • Publication number: 20170317166
    Abstract: Structures that include isolation structures and methods for fabricating isolation structures. First and second trenches are etched in a substrate and surround a device region in which an integrated circuit is formed. A dielectric material is deposited in the first trench to define a first isolation structure, and an electrical conductor is deposited in the second trench to define a second isolation structure.
    Type: Application
    Filed: April 29, 2016
    Publication date: November 2, 2017
    Inventors: Chengwen Pei, Hanyi Ding, Ping-Chuan Wang, Kai D. Feng
  • Patent number: 9800434
    Abstract: Tunable phase shifters and methods for using the same include a signal line; one or more grounding lines; one or more crossing lines below the signal line in proximity to the signal line and substantially perpendicular to a longitudinal direction of the signal line, where the crossing lines conform to the shape of the signal line along at least three surfaces of the signal line and where the crossing lines have a tunable capacitance; and an inductance return line below the crossing lines substantially parallel to the longitudinal direction of the signal line, where the inductance return line provides a tunable inductance.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hanyi Ding, Alberto Valdes Garcia, Wayne H. Woods, Jr.
  • Publication number: 20170227622
    Abstract: The disclosure relates to an apparatus and a method for vector scattering parameter (s-parameter) measurements, and more particularly, to an apparatus and a method for providing a simple, low cost solution for tests requiring vector s-parameter measurements. The apparatus includes a source which provides an input signal, a divider which splits the input signal to a reference signal and a testing signal, a phase shifter which shifts the reference signal by a first phase and outputs a phase shifted signal, a device under test (DUT) which shifts the testing signal by a second phase and outputs a DUT shifted signal, a combiner which combines the phase shifted signal and the DUT shifted signal into a combined signal, and a detector which detects a product of the phase shifted signal and the DUT shifted signal.
    Type: Application
    Filed: February 4, 2016
    Publication date: August 10, 2017
    Inventors: Adem G. AYDIN, Hanyi DING
  • Patent number: 9728838
    Abstract: Approaches for an on-chip antenna are provided. A method includes forming an antenna in an insulator layer at a front side of a substrate. The method also includes forming a trench in the substrate underneath the antenna. The method further includes forming a fill material in the trench. The substrate is composed of a material having a first dielectric constant. The fill material has a second dielectric constant that is less than the first dielectric constant.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: August 8, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hanyi Ding, Mark D. Jaffe, Alvin J. Joseph, Anthony K. Stamper
  • Patent number: 9728603
    Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A base layer comprised of a first semiconductor material is formed. An emitter layer comprised of a second semiconductor material is formed on the base layer. The emitter layer is patterned to form an emitter finger having a length and a width that changes along the length of the emitter finger.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: August 8, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hanyi Ding, Vibhor Jain, Alvin J. Joseph, Anthony K. Stamper
  • Patent number: 9721854
    Abstract: A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Kai D. Feng, Ping-Chuan Wang, Zhijian Yang
  • Patent number: 9599657
    Abstract: Approaches for performing in line wafer testing are provided. An approach includes a method that includes generating a radio frequency (RF) test signal, and applying the RF test signal to a device under test (DUT) in a wafer using a buckling beam probe set with a predefined pitch. The method also includes detecting an output RF signal from the DUT in response to the applying the RF test signal to the DUT, and sensing at least one frequency component of the detected output RF signal.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: March 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hanyi Ding, John Ferrario, Barton E. Green, Stephen Moss, Mustapha Slamani
  • Patent number: 9595936
    Abstract: A reconfigurable bandstop filter and methods of designing and reconfiguring the bandstop filter are disclosed. The reconfigurable bandstop filter includes a plurality of transmission lines each including a phase shifter. The reconfigurable bandstop filter further includes a signal input port having a phase shifter and a signal output port having a phase shifter. The signal input port and the signal output port is coupled to the plurality of transmission lines.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: March 14, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hanyi Ding, Alberto Valdes Garcia, Wayne H. Woods, Jr.
  • Patent number: 9543403
    Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed on the first semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the substrate are etched to define first and second emitter fingers from the second semiconductor layer and trenches in the substrate that are laterally positioned between the first and second emitter fingers. The first semiconductor layer may function as a base layer in the device structure.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hanyi Ding, Vibhor Jain, Qizhi Liu
  • Publication number: 20160372582
    Abstract: Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 22, 2016
    Inventors: Renata Camillo-Castillo, Hanyi Ding, Natalie B. Feilchenfeld, Vibhor Jain, Anthony K. Stamper
  • Publication number: 20160372396
    Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 22, 2016
    Inventors: Hanyi Ding, Vibhor Jain, Alvin J. Joseph, Anthony K. Stamper
  • Publication number: 20160372548
    Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A base layer comprised of a first semiconductor material is formed. An emitter layer comprised of a second semiconductor material is formed on the base layer. The emitter layer is patterned to form an emitter finger having a length and a width that changes along the length of the emitter finger.
    Type: Application
    Filed: June 22, 2015
    Publication date: December 22, 2016
    Inventors: Hanyi Ding, Vibhor Jain, Alvin J. Joseph, Anthony K. Stamper