Abstract: A structure for testing a photodiode in a PIC using a grating coupler in optical communication with an optical terminal in a different location of the photodiode from another optical terminal used during operation of the PIC. The photodiode includes an operational optical terminal and a test optical terminal with the test optical terminal in a different location than the operational optical terminal. An optical component is in optical communication with the operational optical terminal of the photodiode and is used during operation of the photodiode and the PIC. A grating coupler is in optical communication with the test optical terminal of the photodiode for testing purposes.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including an absorber layer separated from an optical grating coupler by a cladding material. The absorber is positioned to receive light reoriented through the optical grating coupler.

Abstract: Structures for a microstrip transmission line and methods of forming a microstrip transmission line. The microstrip transmission line includes a signal line, a shield, and multiple wiring structures connected to the signal line. Each wiring structure extends from a portion of the signal line toward the shield, and each wiring structure includes a metal feature that is positioned adjacent to the shield.

Abstract: Structures for a microstrip transmission line and methods of forming a microstrip transmission line. The microstrip transmission line includes a signal line, a shield, and multiple wiring structures connected to the signal line. Each wiring structure extends from a portion of the signal line toward the shield, and each wiring structure includes a metal feature that is positioned adjacent to the shield.

Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including an absorber layer separated from an optical grating coupler by a cladding material. The absorber is positioned to receive light reoriented through the optical grating coupler.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including an optical medium for light signals; and an optical grating coupler coupled to the optical medium. The optical grating coupler is configured to reorient light from the optical medium. A cladding material is over the optical grating coupler. An absorber layer is over the cladding material, and vertically above the optical grating coupler.

Abstract: Embodiments of the disclosure provide a probe structured for electrical and photonics testing of a photonic integrated circuit (PIC) die, the probe including: a membrane having a first surface and an opposing second surface and including conductive traces, the membrane being configured for electrical coupling to a probe interface board (PIB); a set of probe tips positioned on the membrane, the set of probe tips being configured to send electrical test signals to the PIC die or receive electrical test signals from the PIC die; and a photonic test assembly disposed on the membrane and electrically coupled to the conductive traces of the membrane, the photonic test assembly positioned for substantial alignment with a photonic I/O element of the PIC die, wherein the photonic test assembly is configured to transmit a photonic input signal to the photonic I/O element or detect a photonic output signal from the photonic I/O element.

Abstract: A probe device is configured to insert optical fiber probes directly into a v-groove coupler on an optical integrated circuit (IC) device. The probe device may include a probe holder comprising with a slot. A fiber holder may insert into the slot. The fiber holder may comprise a body with a first portion and second portion disposed at an angle relative to one another so that the first portion is shorter than the second portion. The body may have a bottom with grooves disposed therein, the grooves having dimensions to receive part of an optical fiber probes therein. In use, the fiber holder can arrange the optical fiber probes to extend into the v-grooves of the v-groove coupler of an optical IC on a wafer. The device may incorporate an alignment mechanism that permits the fiber holder to move or “self-align” in response to contact between the optical fiber probes and structure of the v-groove coupler of an optical IC on a wafer.

Abstract: A probe device is configured to insert optical fiber probes directly into a v-groove coupler on an optical integrated circuit (IC) device. The probe device may include a probe holder comprising with a slot. A fiber holder may insert into the slot. The fiber holder may comprise a body with a first portion and second portion disposed at an angle relative to one another so that the first portion is shorter than the second portion. The body may have a bottom with grooves disposed therein, the grooves having dimensions to receive part of an optical fiber probes therein. In use, the fiber holder can arrange the optical fiber probes to extend into the v-grooves of the v-groove coupler of an optical IC on a wafer. The device may incorporate an alignment mechanism that permits the fiber holder to move or “self-align” in response to contact between the optical fiber probes and structure of the v-groove coupler of an optical IC on a wafer.

Abstract: Embodiments of the disclosure provide a probe structured for electrical and photonics testing of a photonic integrated circuit (PIC) die, the probe including: a membrane having a first surface and an opposing second surface and including conductive traces, the membrane being configured for electrical coupling to a probe interface board (PIB); a set of probe tips positioned on the membrane, the set of probe tips being configured to send electrical test signals to the PIC die or receive electrical test signals from the PIC die; and a photonic test assembly disposed on the membrane and electrically coupled to the conductive traces of the membrane, the photonic test assembly positioned for substantial alignment with a photonic I/O element of the PIC die, wherein the photonic test assembly is configured to transmit a photonic input signal to the photonic I/O element or detect a photonic output signal from the photonic I/O element.

Abstract: Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.

Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

Abstract: The disclosure relates to an apparatus and a method for vector scattering parameter (s-parameter) measurements, and more particularly, to an apparatus and a method for providing a simple, low cost solution for tests requiring vector s-parameter measurements. The apparatus includes a source which provides an input signal, a divider which splits the input signal to a reference signal and a testing signal, a phase shifter which shifts the reference signal by a first phase and outputs a phase shifted signal, a device under test (DUT) which shifts the testing signal by a second phase and outputs a DUT shifted signal, a combiner which combines the phase shifted signal and the DUT shifted signal into a combined signal, and a detector which detects a product of the phase shifted signal and the DUT shifted signal.

Abstract: Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.

Abstract: The disclosure relates to an apparatus and a method for vector scattering parameter (s-parameter) measurements, and more particularly, to an apparatus and a method for providing a simple, low cost solution for tests requiring vector s-parameter measurements. The apparatus includes a source which provides an input signal, a divider which splits the input signal to a reference signal and a testing signal, a phase shifter which shifts the reference signal by a first phase and outputs a phase shifted signal, a device under test (DUT) which shifts the testing signal by a second phase and outputs a DUT shifted signal, a combiner which combines the phase shifted signal and the DUT shifted signal into a combined signal, and a detector which detects a product of the phase shifted signal and the DUT shifted signal.

Abstract: Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.

Abstract: A compound resistor structure can use multiple electrically conductive pads connected by resistive elements to provide the equivalent resistance of a conventional resistor while spreading generated heat over a larger area. An array of pads and resistive elements can create larger resistances, metal connectors between rows of pads allowing current to flow from a first pad in a first row to a last pad in a last row via pads and resistive elements in each row. Fuses connecting pads in such an array can be included to allow tuning of resistance and/or other electrical properties.

Abstract: The disclosure relates to an apparatus and a method for vector scattering parameter (s-parameter) measurements, and more particularly, to an apparatus and a method for providing a simple, low cost solution for tests requiring vector s-parameter measurements. The apparatus includes a source which provides an input signal, a divider which splits the input signal to a reference signal and a testing signal, a phase shifter which shifts the reference signal by a first phase and outputs a phase shifted signal, a device under test (DUT) which shifts the testing signal by a second phase and outputs a DUT shifted signal, a combiner which combines the phase shifted signal and the DUT shifted signal into a combined signal, and a detector which detects a product of the phase shifted signal and the DUT shifted signal.

Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.