Patents by Inventor Hao A. Lu
Hao A. Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113195Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.Type: ApplicationFiled: February 22, 2023Publication date: April 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Ni YU, Lung-Kun CHU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
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Patent number: 11950125Abstract: Systems and methods for providing enhanced Quality of Service (QoS) network transmissions can be based on an application sub-class or a user class. Systems and methods can include inspecting the information packet having a network level QoS field having a first network level QoS portion and a second network level QoS portion, determining an application sub-class or user class associated with the information packet, tagging the first network level QoS portion of the information packet according to a first network level QoS value, tagging the second network level QoS portion of the information packet according to a traffic priority indication and to a determined application sub-class or user class, and queuing the information packet for transmission from a network element based on the tagged first network level QoS portion and the second network level QoS portion.Type: GrantFiled: December 22, 2021Date of Patent: April 2, 2024Assignee: Hewlett Packard Enterprise Development LPInventors: Hao Lu, Sachin Ganu, Xiaoding Shang, Nitin Changlani
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Publication number: 20240100790Abstract: An optical element and a method for manufacturing the optical element are described. The optical element includes a transparent substrate, an optical layer, and an adhesive layer. The optical layer is located on a surface of the transparent substrate. The optical layer has a first surface and a second surface, which are opposite to each other. The first surface is set with various diffracting optical structures. A refractive index of the optical layer is equal to or greater than 1.4. The adhesive layer is sandwiched between the surface of the transparent substrate and the second surface of the optical layer.Type: ApplicationFiled: December 6, 2023Publication date: March 28, 2024Inventors: Han Yi KUO, Shu-Hao HSU, Yin Tung LU
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Publication number: 20240100553Abstract: A sprayer, comprising: a container, configured to contain liquid; a passage, comprising a first opening, a second opening, a resonator and a mesh, when the liquid is passed through the resonator, the liquid is emitted as a gas; a first optical sensor, configured to sense first optical data of at least portion of the mesh or at least portion of a surface of the container; and a processing circuit, configured to compute a foaming level of the mesh or of the surface according to the first optical data, and configured to determine whether the resonator should be turned off or not according to the foaming level. In another aspect, the processing circuit estimates a liquid level of the liquid but does not correspondingly turn off the resonator. By this way, the resonator may be turned on or turned off more properly and the liquid level may be more precisely estimated.Type: ApplicationFiled: December 5, 2023Publication date: March 28, 2024Applicant: PixArt Imaging Inc.Inventors: Shih-Jen Lu, Yang-Ming Chou, Chih-Hao Wang, Chien-Yi Kao, Hsin-Yi Lin
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Publication number: 20240099465Abstract: A quick-assembly structure includes an inserting portion and an inserting port allowing the inserting portion to be inserted, where one of the inserting portion and the inserting port is provided on the chassis, and the other one is provided on the back frame. A locking block of the inserting portion is movably arranged relative to the inserting port; and in an assembled state, a bump of the inserting portion is inserted into the inserting port along with the inserting portion, the locking block is pushed by an elastic force of an elastic member of the inserting port to enter a locking position, and at the locking position, a locking end of the locking block enters the inserting port and abuts against an abutting surface of the bump so as to restrict the inserting portion from being pulled out in a direction opposite to an inserting direction thereof.Type: ApplicationFiled: August 17, 2023Publication date: March 28, 2024Applicant: SUNON TECHNOLOGY CO.,LTDInventors: Xujun Zhang, Hao Wu, Changjiang Liu, Xianping He, Aijun Qian, Haibo Lu
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Publication number: 20240100987Abstract: A method for controlling automatic battery swapping of a rail vehicle, includes: receiving vehicle information sent by the rail vehicle; determining whether the rail vehicle has a battery swapping need based on the vehicle information of the rail vehicle; in response to determining that the rail vehicle has the battery swapping need, determining a target battery swapping station according to the battery swapping need; and sending a battery swapping notification signal and a vehicle control signal to the rail vehicle, and sending a battery swapping request signal to the target battery swapping station, where the battery swapping notification signal includes position information of the target battery swapping station, the vehicle control signal controls the rail vehicle to travel to the target battery swapping station, and the battery swapping request signal includes identification information of the rail vehicle and requests the target battery swapping station to swap a battery pack for the rail vehicle.Type: ApplicationFiled: December 11, 2023Publication date: March 28, 2024Inventors: Hao LU, Zhicheng TAN, Hongtao SHE, Mingyang GUO, Keqi ZHANG
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Patent number: 11938974Abstract: A series-parallel monorail hoist based on an oil-electric hybrid power and a controlling method thereof. The monorail hoist includes a cabin, a hydraulic driving system, a lifting beam, a gear track driving and energy storage system, and a speed adaptive control system connected in series with each other and travelling on a track. The monorail hoist is capable of implementing an independent drive by an electric motor or a diesel engine in an endurance mode, a hybrid drive of the electric motor and the diesel engine in a transportation mode, and a hybrid drive of the diesel engine and a flywheel energy storage system in a climbing mode, according to different operating conditions that include conditions of an upslope, a downslope and a load. Power requirements for the monorail hoist under various operating conditions are satisfied, and the excess energy is recovered during the process of travelling.Type: GrantFiled: September 30, 2022Date of Patent: March 26, 2024Assignees: CHINA UNIVERSITY OF MINING AND TECHNOLOGY, XUZHOU LIREN MONORAIL TRANSPORTATION EQUIPMENT CO., LTD.Inventors: Zhencai Zhu, Hao Lu, Yuxing Peng, Gongbo Zhou, Yu Tang, Hua Chen, Zaigang Xu, Mingzhong Wang, Mai Du, Fuping Zheng
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Patent number: 11940659Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.Type: GrantFiled: August 30, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chen-Hao Huang, Hau-Yan Lu, Sui-Ying Hsu, Yuehying Lee, Chien-Ying Wu, Chia-Ping Lai
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Patent number: 11942329Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor protruding structure over a substrate and surrounding the semiconductor protruding structure with an insulating layer. The method also includes forming a dielectric layer over the insulating layer. The method further includes partially removing the dielectric layer and insulating layer using a planarization process. As a result, topmost surfaces of the semiconductor protruding structure, the insulating layer, and the dielectric layer are substantially level with each other. In addition, the method includes forming a protective layer to cover the topmost surfaces of the dielectric layer. The method includes recessing the insulating layer after the protective layer is formed such that the semiconductor protruding structure and a portion of the dielectric layer protrude from a top surface of a remaining portion of the insulating layer.Type: GrantFiled: March 3, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Yi Kao, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
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Patent number: 11942364Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.Type: GrantFiled: July 20, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao
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Patent number: 11943065Abstract: In one configuration, multiple TRPs, or base stations such a next generation node B (gNB) base stations send different transport blocks (TBs) to a user equipment (UE) at the same time or at different times. In another configuration, multiple base stations may send the same data at the same time to a UE. When the same data is being sent by multiple base stations to a UE, the UE must be notified by some mechanism. Disclosed herein are multiple mechanism for notifying the UE that multiple base stations will be transmitting toe same data at the same time. When there is a backhaul between a TRP and another, each TRP can choose to send the same data stream to increase the reliability of the transmission when, for example, the UE receives at a low signal-to-noise ratio (SNR).Type: GrantFiled: May 3, 2021Date of Patent: March 26, 2024Assignee: ZTE CorporationInventors: Chuangxin Jiang, Zhaohua Lu, Yu Ngok Li, Shujuan Zhang, Zhen He, Huahua Xiao, Xinquan Ye, Rongchen Sun, Hao Wu
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Publication number: 20240098487Abstract: A method and apparatus for sending subscriber identifiers are disclosed. The method includes: receiving information of a USIM card from a UICC in a cloud card pool over a first communication connection; receiving an identity request from a 5G SA network, wherein the identity request is for requesting acquiring a SUCI; acquiring the SUCI based on the identity request and the information of the USIM card; and sending the SUCI to the 5G SA network, wherein the SUCI is for establishing a second communication connection. The SUCI may be generated at the ME or at the UICC. The first communication connection may be a roaming communication connection and the second communication connection may be a non-roaming communication connection.Type: ApplicationFiled: October 14, 2021Publication date: March 21, 2024Applicant: HEFEI TUGE TECHNOLOGY CO., LTD.Inventors: LINLIN ZHOU, TIANMING LU, HAO ZHOU, KAIHANG WANG
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Publication number: 20240096994Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.Type: ApplicationFiled: February 10, 2023Publication date: March 21, 2024Inventors: Lung-Kun CHU, Jia-Ni YU, Chun-Fu LU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20240096986Abstract: A method includes forming a first gate spacer and a second gate spacer on a sidewall of a first gate structure. The first gate spacer is between the second gate spacer and the first gate structure. A first interlayer dielectric (ILD) layer is formed to surround the first gate spacer, the second gate spacer, and the first gate structure. A portion of the second gate spacer and a portion of the first ILD layer are removed simultaneously. A top surface of the second gate spacer is lower than a top surface of the first ILD layer.Type: ApplicationFiled: December 1, 2023Publication date: March 21, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Ting LI, Jen-Hsiang LU, Chih-Hao CHANG
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Publication number: 20240097071Abstract: Disclosed in the present application are a display substrate, a preparation method therefor, and a display device. The display substrate includes a rigid substrate, and a flexible film layer and a display function layer that are sequentially stacked on the rigid substrate. The rigid substrate is provided with an opening at a bending region to expose the flexible film layer in the bending region. The display substrate further includes a first light absorption portion in a display region and is on the side of the display region close to the bending region. The first light absorption portion is on the side of the rigid substrate facing away from the flexible film layer or is between the rigid substrate and the flexible film layer.Type: ApplicationFiled: January 25, 2021Publication date: March 21, 2024Inventors: Xinhong LU, Xiaoyan ZHU, Qi QI, Hao CHEN
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Patent number: 11937234Abstract: Provided are an information transmission method and a relevant device. The method includes: a terminal receiving first signaling and second signaling, where the first signaling is configured for indicating a transmission configuration indication (TCI) state, and the second signaling is configured for triggering a first reference signal indicated in the TCI state; and the terminal determining, according to the first signaling, a target channel or a target signal scheduled by the first signaling, where the target channel or the target signal scheduled by the first signaling uses quasi-co-location (QCL) information corresponding to the first reference signal transmitted before a first symbol or QCL information corresponding to the second signaling transmitted before a first symbol.Type: GrantFiled: September 20, 2019Date of Patent: March 19, 2024Assignee: ZTE CorporationInventors: Hao Wu, Bo Gao, Chuangxin Jiang, Shujuan Zhang, Zhaohua Lu, Yijian Chen, Yu Ngok Li
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Patent number: 11930843Abstract: A cartridge assembly may be utilized in combination with an electronic nicotine delivery system for the safe, efficient and cost-effective means for delivering a controlled dose of nicotine to a user on demand. The cartridge assembly includes a reservoir with a material for holding liquid nicotine or a liquid nicotine solution and is constructed from a material that is chemically resistant to nicotine or nicotine solution. The cartridge assembly includes an anti-counterfeit feature to prevent use of an unauthorized cartridge in the electronic nicotine delivery system. The cartridge assembly also includes an anti-reuse feature that precludes reuse of the cartridge assembly once removed from the electronic nicotine delivery system. Essentially, the cartridge assembly is designed for a single use only.Type: GrantFiled: February 5, 2019Date of Patent: March 19, 2024Assignee: McNeil ABInventors: Corrado Tasselli, Cheng-Hsien Lu, Chun-Hao Hsu
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Publication number: 20240085611Abstract: A front light module includes a light guide sheet and a light bar. The light guide sheet has two light receiving laterals, a fold line, a first pattern area, and a second pattern area respectively located on two sides of the fold line. One light receiving lateral is protruded to form first taper sets, and the other is protruded to form second taper sets. The second pattern area is superimposed on the first pattern area, and the first and second tapers set are engaged and coplanar to form a light incident surface after folding along the fold line. The light bar provides light toward the light incident surface, the first pattern area is lit by the odd positions of the light bar via the first taper sets, and the second pattern area is lit by the even positions of the light bar via the second taper sets.Type: ApplicationFiled: June 8, 2023Publication date: March 14, 2024Inventors: JIN-WEI TONG, HAO LU, FAN-WEI WU, WEI-LUN HUANG
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Publication number: 20240088022Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.Type: ApplicationFiled: November 17, 2023Publication date: March 14, 2024Inventors: Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao
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Publication number: 20240088193Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a substrate and a wafer disposed on the substrate. The wafer includes a p-doped layer disposed on the substrate; a first diode disposed on the p-doped layer; a second diode disposed on the p-doped layer; a third diode disposed on the p-doped layer; and a dielectric layer disposed on the substrate and covering the first, second, and third diodes. The first, second, and third diodes are disposed side by side.Type: ApplicationFiled: January 12, 2023Publication date: March 14, 2024Inventors: CHUN-LIANG LU, CHUN-HAO CHOU, KUO-CHENG LEE