Patents by Inventor Hao An

Hao An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160300326
    Abstract: This invention discloses an image processing device and an image processing method. The image processing device includes a line buffer, a pixel enhancing module, a smoothing module, a noise reduction module and a contrast adjusting module. The line buffer stores a plurality of pixel values of an image. The pixel enhancing module performs an edge-enhancing operation on the image. The smoothing module filters the image to improve the image in terms of roughness. The noise reduction module filters the image to improve the image in terms of a signal-to-noise ratio. The contrast adjusting module checks whether a target pixel is on a thin edge to decide the method of adjusting the contrast of the image.
    Type: Application
    Filed: December 16, 2015
    Publication date: October 13, 2016
    Inventors: HAO-TIEN CHIANG, SHIH-TSE CHEN
  • Publication number: 20160301567
    Abstract: Embodiments of the present invention provide a system upgrade method and device, which can reduce a quantity and a time of service interruptions when an ONT and an OLT are upgraded. The method includes: detecting an upgrade triggering event, where the upgrade triggering event is used to instruct an optical network terminal ONT and an optical line terminal OLT to perform a concurrent upgrade; resetting the ONT to activate a preloaded ONT upgrade program; and restoring a service with the OLT. According to the embodiments of the present invention, an ONT and an OLT basically concurrently or synchronously perform upgrading and resetting, that is, a concurrent upgrade, so that a quantity and a time of service interruptions caused when the ONT and the OLT are upgraded are reduced, thereby improving user experience.
    Type: Application
    Filed: June 22, 2016
    Publication date: October 13, 2016
    Inventors: Fuwang ZHANG, Hao ZHANG
  • Publication number: 20160297721
    Abstract: Provided is a processing apparatus for quick resource recovery of kitchen garbage, configured as a fully enclosed silo and comprising: a transportation chain configured to drive a charger to lift up and down with a feed port correspondingly disposed above the transportation chain, shredder blades being provided within the feed port to shred materials; a fermentation chamber below the shredder blades, a main stirring shaft being horizontally provided within the fermentation chamber, two secondary stirring wheels being provided on the main stirring shaft at two respective side walls of the fermentation chamber, at the respective side walls the main stirring shaft is connected onto the fermentation chamber the main stirring shaft configured to be rotated in a direction opposite to that of the secondary stirring wheels; the main stirring shaft being provided with stirring paddles; a spiral discharger horizontally provided below the main stirring shaft and provided with a discharge port at one end thereof; a deodo
    Type: Application
    Filed: April 1, 2015
    Publication date: October 13, 2016
    Inventors: Mingxiao LI, Jiaqi HOU, Beidou XI, Yan HAO, Chaowei ZHU, Yonghai JIANG, Xuan JIA
  • Publication number: 20160301611
    Abstract: The present invention discloses a method for avoiding congestion on a network device and a network device, in order to resolve a problem of a decrease in a throughput of a network device caused when the network device performs, after receiving a series of packets, packet discarding processing on the series of packets in a manner of randomly and discretely discarding packets. The method includes: determining, by a network device according to a size of currently used storage space, whether packet discarding processing needs to be performed on packets that belong to a same data flow in the currently used storage space, where there are N packets that belong to the same data flow, and N?2; and if packet discarding processing needs to be performed, discarding, by the network device, continuous M packets that belong to the same data flow, where 1?M?N.
    Type: Application
    Filed: June 10, 2016
    Publication date: October 13, 2016
    Inventors: Jin LI, Lei HAN, Hao WANG
  • Publication number: 20160296564
    Abstract: The present invention provides modified natural killer T (NKT) cells, pharmaceutical compositions comprising the modified NKT cells and at least one pharmaceutically acceptable carrier or excipient, and uses of the modified NKT cells. Also disclosed herein are methods for enriching NKT cells and generating the modified natural killer T cells.
    Type: Application
    Filed: April 6, 2016
    Publication date: October 13, 2016
    Inventors: Jan-Mou LEE, Chih-Hao FANG, Ya-Fang CHENG, Da-Tsen WEI, Kai-Yuan JHOU
  • Publication number: 20160300659
    Abstract: A power module includes a magnetic component and a switch component. The magnetic component includes a magnetic core, and a winding disposed in the magnetic core. An end of the winding forms a pin of the power module for electrically connecting to an external circuit. The switch component is electrically connected to the magnetic component. An I/O pin of the power module may be formed from an end of the winding, such that a bonding/contact resistance of connecting the power module to the external circuit can be reduced.
    Type: Application
    Filed: March 24, 2016
    Publication date: October 13, 2016
    Inventors: Yu ZHANG, Shou-Yu HONG, Hao-Yi YE, Jian-Hong ZENG
  • Publication number: 20160302225
    Abstract: A method, an apparatus, and a computer program product for wireless communication are provided. An eNB transmits an indicator for a frame identifying a DL transmission period. The indicator may comprise a frame format indicator identifying only a plurality of downlink subframes scheduled for a contention-based carrier. The eNB may transmit a second indicator for an UL transmission period and may grant a UE at least one UL subframe for UL transmission. The UE monitors for an UL grant and for a D-CUBS at either the end of the DL subframes or after an UL assignment. The eNB may transmit a provisional grant UL assignment for UL transmission on an SCC and respond with a grant confirmation in response to an SR granting the UE resources for UL data transmission.
    Type: Application
    Filed: March 16, 2016
    Publication date: October 13, 2016
    Inventors: Aleksandar DAMNJANOVIC, Tao LUO, Srinivas YERRAMALLI, Peter GAAL, Hao XU, Wanshi CHEN
  • Publication number: 20160299984
    Abstract: An input method editor (IME) described herein couples scenarios of the input of the user with specific network services to offer more relevant and richer candidates for higher input productivity. Data relating to a computer application in which the input candidates are to be input and/or context relating to a user-submitted query is collected and analyzed to determine a scenario. The input candidates may include text candidates and rich candidates. The IME may select a scenario-tuned and type specific engine to identify the text candidates and/or rich candidates. The scenario-tuned text candidate engines leverage scenario-tuned language models and lexicons, and the scenario-tuned rich candidate engines leverage scenario-relevant web services, such as image, mapping, and video search, when available and appropriate.
    Type: Application
    Filed: June 22, 2016
    Publication date: October 13, 2016
    Inventors: Matthew Robert Scott, Huihua Hou, Weipeng Liu, Hao Wei, Chiwei Che, Byron Huntley Changuion, Weijiang Xu, Xi Chen
  • Patent number: 9466592
    Abstract: A multi-chips in system level and wafer level package structure includes a package substrate having a plurality of through holes a multi-chips with different functions and sizes, the metal wires, a package body, and the conductive components. The multi-chips are used to combine with the package substrate so as to the pads of the multi-chips are exposed out of the through holes. The pads of the multi-chips are electrically connected to the connecting terminal adjacent to the through holes by the plurality of conductive wires. The package material is filled into the through holes to form the package body to encapsulate the conductive wire, each active surface and the pads of the multi-chips with the different functions and the sizes by dispensing method so as to the multiple chip system level and wafer level package structure is accomplished by partially packaging method.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: October 11, 2016
    Assignee: GAINIA INTELLECTUAL ASSET SERVICES, INC.
    Inventors: Shih-Chi Chen, Hao-Pai Lee
  • Patent number: 9467954
    Abstract: Disclosed are a power adjustment method and an apparatus based on low delay power detection before digital pre-distortion. The method comprises the following steps: according to pre-configured system carrier information, obtaining effective carrier information containing an effective carrier channel corresponding to each effective carrier; performing sampling on carrier data of each effective carrier channel according to the obtained effective carrier information, and then calculating combination power Pa of effective carriers before digital up conversion or digital peak clipping cancellation according to the sampling; and using the combination power Pa of the effective carriers to perform power adjustment before digital pre-distortion. The present invention moves power calculation ahead of an up conversion module, fully utilizes inherent delay of digital up conversion and a peak clipping module to offset time required for the power calculation, and effectively reduces system delay.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: October 11, 2016
    Assignee: ZTE Corporation
    Inventors: Zhen Cao, Hao Qiu, Wei Chen, Cong Xiao, Xuelong Yuan
  • Patent number: 9464576
    Abstract: A system including a fuel-supply system including, an auxiliary-fuel-gas compressor configured to compress a fuel for use by a gas-turbine system, an expander configured to generate power by expanding an oxidant from the gas-turbine system, and a motor/generator configured to function in a motor mode and in a generator mode, wherein the motor/generator drives fuel compression with the auxiliary fuel-gas compressor in the motor mode, and the motor/generator generates power in the generator mode as the expander uses oxidant from the gas-turbine system to drive the motor/generator.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: October 11, 2016
    Assignee: General Electric Company
    Inventors: Hua Zhang, Wenjie Wu, Yongjiang Hao
  • Patent number: 9466438
    Abstract: The present invention provides a touch panel. The touch panel includes first sensing lines extending in a first direction, second sensing lines extending in a second direction and intersecting with the first sensing lines, an insulating pad disposed at each intersection between the first sensing lines and the second sensing lines for isolating the first sensing lines and the second sensing lines. A direction of an external force exerted in the insulating pad is non-perpendicular to the edge of said insulating pad on the same horizontal plane. The present invention also provides a manufacturing method of the touch panel. The design of the insulating pad can disperse the external impact force caused by air knife, washing and so on, and preventing the cut-off of the insulating pad, thereby improving the yield of the touch panel.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: October 11, 2016
    Assignee: TPK TOUCH SOLUTIONS (XIAMEN) INC.
    Inventors: Chan-Hao Tseng, Hsien-Jung Li, Cheng-Chung Chiang
  • Patent number: 9464435
    Abstract: Disclosed are a metal curtain wall system of a monolayer structure and a construction method thereof. The metal curtain wall system comprises a plurality of composite material curtain wall units (1) that are produced in a numerical control manner and have complex models. The plurality of composite material curtain wall units (1) is spliced to form an inner-outer wall body model. Embedded members (2) are arranged in the composite material curtain wall units (1). Lead-out parts of the embedded members are oriented towards the inner and outer wall bodies and are fixed to inner and outer wall bodies. The composite material curtain wall units (1) in vertical adjacency are arrayed in a staggered manner. An elastic structural adhesive (3) is coated on surfaces of the composite material curtain wall units (1). Thin-type metal sheets (4) are covered on the elastic structural adhesive (3).
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 11, 2016
    Assignee: Evergrow International Trading (Shanghai) Co., Ltd.
    Inventors: Chuan Hul Ku, Wen Hao Ku
  • Patent number: 9466598
    Abstract: A semiconductor structure suitable for ESD protection application is provided. The semiconductor structure includes a first well, a second well, a third well, a first fin, a second fin, an anode, a cathode and a first doping region. The first well and the second well are disposed in the third well. The first fin is disposed on the first well. The second fin is disposed on the second well. The anode is disposed on the first fin. The cathode is disposed on the second fin. The first doping region is disposed under the first fin, and separates the first fin from the first well. The first well, the second well, the first fin and the second fin have a first doping type. The third well and the first doping region have a second doping type.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Cheng Liao, Yu-Chun Chen, Ping-Chen Chang, Tien-Hao Tang
  • Patent number: 9466392
    Abstract: A memory array includes a first memory page and a second memory page. The first memory page includes a first word line, a first select gate line, a first control line, a first erase line, and a plurality of first memory cells each coupled to the first word line, the first select gate line, the first control line, and the first erase line, and for receiving a bit line signal and a source line signal. The second memory page includes a second control line, a second erase line, and a plurality of second memory cells each coupled to the first word line, the first select gate line, the second control line, and the second erase line, and for receiving a bit line signal and a source line signal.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: October 11, 2016
    Assignee: eMemory Technology Inc.
    Inventors: Wei-Chen Chang, Wen-Hao Ching, Chih-Hsin Chen, Shih-Chen Wang, Ching-Sung Yang
  • Patent number: 9466930
    Abstract: A plug connector mateable with the receptacle connector, includes an insulative housing enclosed in a metallic shell, defining a receiving cavity to receive the mating tongue, and equipped with a plurality of contacts on opposite sides in the vertical direction. A latch forms a pair of locking heads extending into two opposite lateral sides of the receiving cavity to lock with a shielding plate embedded within a mating tongue of the complementary receptacle connector during mating.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: October 11, 2016
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Terrance F. Little, Chih-Pi Cheng, Wei-Hao Su, Cheng-Chi Yeh, Yuan Zhang, Ming-Lun Szu, Chi-Tung Kuan
  • Patent number: 9466249
    Abstract: A display and an operating method thereof are provided. The display includes a display panel, a timing controller, and a plurality of source drivers. The source drivers are coupled to the timing controller and the display panel, and the source drivers are coupled to one another. The timing controller outputs a plurality of training packets to the source drivers. When the source drivers lock a clock of the timing controller according to the training packets, a lock signal is output to the timing controller. The timing controller outputs a plurality of color data packets and at least one latch signal to the source drivers based on the lock signal. The source drivers respectively output a plurality of pixel voltages to the display panel according to the latch signal. The training packets and the color data packets are serially transmitted to the source drivers.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: October 11, 2016
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Hsin-Chia Su, Jia-Hao Wu, Chin-Tien Chang
  • Patent number: 9466730
    Abstract: The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 11, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Rahul Kumar, Manoj Kumar, Gene Sheu, Shao-Ming Yang, Rudy Octavius Sihombing, Chia-Hao Lee, Shang-Hui Tu
  • Patent number: 9467162
    Abstract: A switched capacitor digital-to-analog converter (“DAC”) for converting a digital input code to an analog signal comprises a switched capacitor array and a reset switch having a first end and a second end. The digital input code is inputted to the switched capacitor array. The switched capacitor array is connected to a summation node. The first end of the reset switch is connected to the summation node and the second end of the reset switch is connected to a common mode voltage. The reset switch is closed after a plurality of sampling cycles. The analog signal is provided based on a summation voltage at the summation node.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: October 11, 2016
    Assignee: Amlogic Co., Limited
    Inventors: Hao Zhu, Kai Fan, Xiaoniu Luo, Chieh-Yuan Chao
  • Patent number: D768579
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: October 11, 2016
    Assignee: Siemens Aktiengesellschaft
    Inventors: Chang Sen Chen, Jie Yang, Yu Hao Zhu