Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

Abstract: A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

Abstract: A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.

Abstract: Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes an isolation layer formed around the first fin structure and covering a sidewall of the first fin structure and a gate stack formed over the first fin structure and the isolation layer. The semiconductor device structure further includes a first source/drain structure formed over the first fin structure and spaced apart from the gate stack and a contact structure formed over the first source/drain structure. The semiconductor device structure includes a dielectric structure formed through the contact structure. In addition, the contact structure and the dielectric structure has a first slope interface that slopes downwardly from a top surface of the contact structure to a top surface of the isolation layer.

Abstract: A quick no-water startup apparatus for a centrifugal pump includes, from top to bottom in sequence, one-way passages (1), a self-priming chamber housing (41), sliding devices (5), a self-priming chamber (4), chamber partition plates (2) a concave-convex impeller (3), inlet channels (6) connected on two sides of the self-priming chamber (4), a spring device (7) of an upper-side x-shaped gas-liquid separation device, the upper-side x-shaped gas-liquid separation device (8), upper and middle-side gas-liquid separation device connecting shafts (9), a middle-side gas-liquid separation device (10), lower-side backflow-type gas-liquid separation devices (11), v-shaped backflow channels (122), an inverted v-shaped inlet channel (121), and an inlet.

Abstract: A cryo formulation-based microneedle device for transdermal delivery of bioactive therapeutic agents. The microneedle device includes: one or more microneedle patches each including an array of miniaturized needles, wherein each miniaturized needle defining a base end and a tip; and a substrate to which the base end of the array of miniaturized needles is attached or integrated thereto; wherein the microneedle patch is in a cryo status; wherein each of the one or more microneedle patch is adapted to be applied on a skin surface, in which the miniaturized needles penetrates into skin; wherein the miniaturized needles is further arranged to melt so as to release one or more bioactive therapeutic agents into the skin to achieve a targeted therapeutic effect; and wherein the bioactive therapeutic agents includes protein and/or antigens.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a gate structure formed over a substrate, and a first source/drain (S/D) structure formed adjacent to the gate structure. The semiconductor structure includes an S/D contact structure formed over the first S/D structure, and a dielectric wall formed below the gate structure and the S/D contact structure. The dielectric wall has a first portion directly below the S/D contact structure and a second portion directly below the gate structure, the first portion has a first height along a vertical direction, the second portion has a second height along the vertical direction, and the first height is smaller than the second height.

Abstract: A method of forming a semiconductor device includes forming a dummy gate structure across a fin protruding from a substrate, forming gate spacers on opposite sidewalls of the dummy gate structure, forming source/drain epitaxial structures on opposite sides of the dummy gate structure, forming a first interlayer dielectric (ILD) layer on the source/drain epitaxial structures and outer sidewalls of the gate spacers, replacing the dummy gate structure with a replacement gate structure, etching back the replacement gate structure to form a first recess between the gate spacers, forming a source/drain contact in the first ILD layer, and forming a second interlayer dielectric (ILD) layer to fill in the first recess between the gate spacers and over the source/drain contact.

Abstract: A method includes performing a lithography process using a mask and a pellicle membrane; detaching the pellicle membrane from the mask after the lithography process is completed; performing an inspection process to the pellicle membrane, the inspection process including generating a laser beam toward the pellicle membrane from a laser source, such that the laser beam passes through the pellicle membrane; and generating an image by receiving the laser beam passing through the pellicle membrane using an image sensor; and determining whether a particle is present on the pellicle membrane or a pin hole is present in the pellicle membrane based on the image.

Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor, a conductive feature on the transistor, a dielectric layer over the conductive feature, and an electrical connection structure in the dielectric layer and on the conductive feature. The electrical connection structure includes a first grain of a first metal material and a first inhibition layer extending along a grain boundary of the first grain of the first metal material, the first inhibition layer is made of a second metal material, and the first metal material and the second metal material have different oxidation/reduction potentials.

Abstract: The present application relates to the technical field of polyaryletherketone, and discloses a preparation method for a coating material containing high-temperature self-crosslinking fluorine-containing polyaryletherketone. A molecular chain of the high-temperature self-crosslinking fluorine-containing polyaryletherketone contains two crosslinking groups of a styrene group and a thioether group, and its structural formula is: Herein, the value range of m is 1-40%, the value range of n is 60-99%, and R is a group that removes a phenolic hydroxyl group from hexafluorobisphenol A. In the high-temperature curing process after film coating, the crosslinking reaction occurs to form a crosslinked polymer coating layer, thereby a coating surface with good moisture and heat resistance, wear resistance, and low friction coefficient is formed.

Abstract: A device comprises a display that includes an aperture layer, a plurality of light sources, and a piezo material. The aperture layer includes a plurality of apertures. The plurality of light sources is arranged to correspond to the plurality of the aperture. The piezo material is coupled to the light sources and is configured to alter a distance between the light sources and the corresponding apertures.

Abstract: An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.

Abstract: An antenna structure and an electronic device are provided. The antenna structure includes a substrate with opposing first and second surfaces, a first radiating element with a first radiating portion and a second radiating portion, a third radiating portion, a feeding portion, and a grounding portion that are connected to the first radiating portion, a second radiating element separate from but coupling with the first radiating portion, a grounding element connected to the grounding portion, and a feeding element. The first radiating portion, the feeding portion, and the grounding portion are disposed on the first surface. The second radiating portion and the third radiating portion are disposed on the second surface. A projected area of the second radiating portion onto the first surface partially overlaps with the feeding portion. A projected area of the third radiating portion onto the first surface partially overlaps with the grounding portion.

Abstract: A video encoding method includes: during a first period, performing an encoding process upon a first block group of a current frame to generate a first block group bitstream; and during a second period, transmitting a second block group bitstream derived from encoding a second block group of the current frame, wherein the second period overlaps the first period. The encoding process includes: during a first time segment of the first period, performing a first in-loop filtering process upon a first group of pixels; and during a second time segment of the first period, performing a second in-loop filtering process upon a second group of pixels, wherein the second time segment overlaps the first time segment, and a non-zero pixel distance exists between a first edge pixel of the first group of pixels and a second edge pixel of the second group of pixels in a filter direction.

Abstract: Security devices and methods for regulating access to an item secured within the security device are provided. In an example, the method includes: determining if a requesting user submitting a request to access the item is an authorized user; and in response to determining the requesting user is the authorized user, the method further includes one or more actions of: triggering a predefined wait period; allowing the requesting user access to the item and notifying at least one of a primary user, a designated user, or a third party service; or notifying the at least one of the primary user, the designated user, or the third party service that the requesting user is requesting access to the item, and receiving an approval or a denial of access to the item to the requesting user from at least one of the primary user, the designated user, or the third party service.

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

Abstract: An electronic device is provided by the present disclosure. The electronic device includes a substrate; a first transistor disposed on the substrate and including a first semiconductor layer and a gate electrode; a first insulating layer disposed between the first semiconductor layer and the gate electrode; a second insulating layer disposed on the first insulating layer, wherein the first semiconductor layer and the gate electrode are located between the substrate and the second insulating layer; a barrier layer disposed on the second insulating layer; and a second transistor disposed on the barrier layer and including a second semiconductor layer, wherein the barrier layer is disposed between the second semiconductor layer and the second insulating layer.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.