Patents by Inventor Hao Chen

Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200004917
    Abstract: A method of forming an integrated device includes: pre-storing a plurality of via pillars in a storage tool; arranging a first via pillar selected from the plurality of via pillars to electrically connect to a circuit cell in a first circuit; analyzing an electromigration information of the first circuit to determine if the first via pillar induces EM phenomenon; arranging a second via pillar selected from the plurality of via pillars to replace the first via pillar of the circuit cell to generate a second circuit when the first via pillar induces EM phenomenon; and generating the integrated device according to the second circuit.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: CHUN-YAO KU, WEN-HAO CHEN, MING-TAO YU, SHAO-HUAN WANG, JYUN-HAO CHANG
  • Publication number: 20200001184
    Abstract: A system, a machine-readable storage medium storing instructions, and a computer-implemented method are described herein for a System Tuner for defining an in-game event requiting accumulation of a pre-defined set of virtual objects in a virtual game (or online game) prior to termination of the in-game event. The System Tuner determines a head-start subset from the pre-defined set of virtual objects for a target player account based on a difference between a reference player skill level for the virtual game and a player skill level of the target player account. The System Tuner determines, based on the player skill level of the target player account and a pre-defined duration of the in-game event, a drop rate for virtual objects remaining in the pre-defined set of virtual objects. The System Tuner sends the head-start subset and the drop rate to a client device associated with the target player account.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Stan Patton, Jean Luo, Jack Lim, Tim LeTourneau, Alexi Chialtas, Joseph Traverso, Hao Chen
  • Patent number: 10522521
    Abstract: An illumination assembly includes a substrate, a wiring structure, a reflecting layer and a plurality of light-emitting diodes. The wiring structure is formed on a part of the substrate, and includes a catalyst layer covering the part of the substrate, and a conducting layer formed on the catalyst layer. The reflecting layer is formed on another part of the substrate that is exposed from the wiring structure. The light-emitting diodes are disposed on the wiring structure and are electrically connected to the wiring structure.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 31, 2019
    Assignee: Taiwan Green Point Enterprises Co., Ltd.
    Inventors: Yu-Chuan Lin, Pen-Yi Liao, Hui-Ching Chuang, Chih-Hao Chen, Ai-Ling Lin
  • Patent number: 10522956
    Abstract: The present disclosure discloses an electronic device including an electronic apparatus and an electric connector. The electronic apparatus includes an electric connection port. The electric connection port includes a concave trench, a first and second conductive strips are disposed in the concave trench. The first conductive strip and the second conductive strip respectively extend along an extending direction of the concave trench. The electric connector includes a first and second elastic contacts which are exposed and protruded outward. When the electric connector is plugged into the electric connection port, the first elastic contact is in contact with the first conductive strip, and the second elastic contact is in contact with the second conductive strip. The electric connection port may accommodate the electric connector, so that the electric connector may be selectively plugged to any position on the electric connection port along the extending direction of the concave trench.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 31, 2019
    Assignee: PEGATRON CORPORATION
    Inventors: Yi-Wei Lee, Hsien-Tsung Lee, Shih-Hao Chen
  • Publication number: 20190393325
    Abstract: Embodiments disclosed herein relate generally to forming a structure, e.g., in high aspect ratio trenches. In an embodiment, a method for semiconductor processing is provided. The method includes forming fins on a substrate. Sidewalls of the fins and a bottom surface between the sidewalls of the fins define a trench therebetween. The method includes forming a gate structure over the fins. The gate structure has a sidewall with a defect region formed therein. The method includes forming a filling layer to fill the defect region in the sidewall of the gate structure.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Inventors: Chia-Ao Chang, Chien-Hao Chen, De-Wei Yu, Yung-Cheng Lu
  • Publication number: 20190391607
    Abstract: A voltage adjustment device comprises a voltage detector and a signal emitter. The voltage detector electrically connects to an electrical device through a power rail and obtains a voltage detected value of the power rail. The signal emitter electrically connects to the voltage detector and is configured to electrically connect to a host and a power board. The signal emitter generates a power good signal and sends the power good signal to the host when the voltage detected value is larger than a baseline voltage value for the first time. After sending the power good signal, the signal emitter generates a voltage adjustment signal according to the voltage detected value and is configured to send the voltage adjustment signal to the power board for selectively adjusting a voltage provided by the power board.
    Type: Application
    Filed: September 12, 2018
    Publication date: December 26, 2019
    Applicant: WIWYNN CORPORATION
    Inventors: Yi-Hao CHEN, Chia-Ming TSAI
  • Publication number: 20190394845
    Abstract: A current source circuit and an LED driving circuit applying the same. A current at an output terminal of an operational transconductance amplifier is shunted based on a first control signal that includes duty cycle information, or an input signal at at least one input terminal of the operational transconductance amplifier is controlled to be switched between different voltage signals based on the first control signal, so as to adjust an output current of a current adjustment circuit. A driving voltage for driving a current generation circuit is adjusted based on the output current. Thereby, a driving current generated by the current source circuit is correlated with the duty cycle information. An amplitude modulation circuit used, a low-pass filter and the like for processing the first control signal are not used, effectively simplifying circuit design and improving system efficiency.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 26, 2019
    Applicant: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD
    Inventor: Hao CHEN
  • Publication number: 20190393297
    Abstract: A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 26, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Yuan KUNG, Chien-Hua CHEN, Teck-Chong LEE, Hung-Yi LIN, Pao-Nan LEE, Hsin Hsiang WANG, Min-Tzu HSU, Po-Hao CHEN
  • Patent number: 10516659
    Abstract: The present disclosure provides a user information obtaining method and apparatus, and a server.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: December 24, 2019
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Hao Chen, Maowei Yang
  • Patent number: 10517020
    Abstract: A user equipment (UE) context migration management method applied to a mobile edge platform for managing a UE context of a mobile communication device is provided. An embodiment of the UE context migration management method includes: receiving at least one migration request for the UE context; calculating a first difference data corresponding to the UE context in response to the at least one migration request, wherein the first difference data represents a difference between the UE contexts obtained in two consecutive UE context retrieving operations corresponding to the at least one migration request; and transmitting the first difference data to the neighboring mobile edge platform to request the neighboring mobile edge platform to perform a migration operation of the UE context based on the first difference data.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: December 24, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kuo-Wei Wen, Chun-Chieh Wang, Jian-Hao Chen
  • Patent number: 10515803
    Abstract: An embodiment is a method of fabricating a semiconductor structure. The method includes utilize uses of a multi-layer structure disposed on a pattern defining layer. In some embodiments, a method of fabricating a semiconductor structure includes forming a first multi-layer structure on a pattern defining layer disposed on a film stack on a substrate, patterning the first multi-layer structure to form an aperture in the first multi-layer structure, forming a first cut opening in the pattern defining layer through the aperture defined by the first multi-layer structure, and forming a second multi-layer structure on the pattern defining layer, a portion of the second multi-layer structure being disposed in the first cut opening.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiann-Horng Lin, Yi-Chang Lee, Che-Kang Chu, Chih-Hao Chen
  • Patent number: 10515186
    Abstract: A method of decomposing a layout for multiple-patterning lithography includes receiving an input that represents a layout of a semiconductor device. The layout includes a plurality of conductive lines of a cell. A first set of conductive lines are overlaid by a second set of conductive lines. The method further includes partitioning the second set of conductive lines into groups. A first group has a different number of conductive lines from the second set than a second group. The method further includes assigning conductive lines from the first set overlaid by conductive lines of the first group to a first photomask and assigning conductive lines from the first set overlaid by conductive lines of the second group to second and third photomasks.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Meng-Kai Hsu, Wen-Hao Chen
  • Patent number: 10516048
    Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Chih Chen, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
  • Patent number: 10516342
    Abstract: A three arm rectifier and inverter circuit is provided. The three arm rectifier and inverter circuit includes an input end, a rectifier circuit and an inverter circuit. The input end is utilized for inputting an input voltage and an input current. The rectifier circuit includes a low frequency switching arm. The low frequency switching arm is coupled to the input end for receiving the input voltage and the input current and generating a trigger signal. The inverter circuit includes a full bridge switch. The full bridge switch is coupled to the low frequency switching arm for receiving the trigger signal and adjusting an output voltage.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: December 24, 2019
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Kun-Feng Chen, Jun-Hao Chen, Hsu-Pin Yang
  • Patent number: 10514089
    Abstract: An auxiliary oil pump system for a gearbox, comprising: an auxiliary battery; a controller electrically connected to the auxiliary battery; and an auxiliary oil pump driven by the controller using a self-adaptive process, wherein the self-adaptive process comprises: the controller receives current operational pressure signal and compared the current operational pressure signal to a pressure threshold; if the current operational pressure signal is bigger than the pressure threshold, the auxiliary oil pump keeps current rotational speed; if the current operational pressure signal is smaller than the pressure threshold, the auxiliary oil pump improves the rotational speed by a pre-determined speed.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: December 24, 2019
    Assignee: Johnson Electric International AG
    Inventors: Rui Feng Qin, Xiao Ming Wang, Ping Hua Tang, Hao Chen, Lei Jiang, Zhi Yang Zhong, Nian He Qu
  • Patent number: 10515963
    Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Hao Liu, Yan-Ming Tsai, Chung-Ting Wei, Ziwei Fang, Chih-Wei Chang, Chien-Hao Chen, Huicheng Chang
  • Publication number: 20190387323
    Abstract: Disclosed are a diaphragm and a loudspeaker using the diaphragm. The diaphragm comprises an edge, a fixing section formed by the edge's outer edge extending outward, and an intermediate section formed by the edge's inner edge extending inward, wherein the edge is disposed with a plurality of stiffeners extending from the edge and across the edge's inner edge to the intermediate section. The loudspeaker includes the diaphragm. The stiffeners disposed on the edge extend to the intermediate section, which increases strength of the inner of the edge, especially of the curved sections. In this way, strength of the edge and stability and pure tone matters of the diaphragm during practical applications may be improved.
    Type: Application
    Filed: June 12, 2019
    Publication date: December 19, 2019
    Inventor: Hao Chen
  • Publication number: 20190384172
    Abstract: Resist materials having enhanced sensitivity to radiation are disclosed herein, along with methods for lithography patterning that implement such resist materials. An exemplary resist material includes a polymer, a sensitizer, and a photo-acid generator (PAG). The sensitizer is configured to generate a secondary radiation in response to the radiation. The PAG is configured to generate acid in response to the radiation and the secondary radiation. The PAG includes a sulfonium cation having a first phenyl ring and a second phenyl ring, where the first phenyl ring is chemically bonded to the second phenyl ring.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Inventors: Yen-Hao Chen, Wei-Han Lai, Chien-Wei Wang, Chin-Hsiang Lin
  • Patent number: 10509929
    Abstract: The invention discloses a scan head's aiming beam exposure solution system, comprising the control circuit of aiming lamp. The control circuit is composed of 5 pin terminals, wherein pin 1 and 2 are the input terminal of gate circuit, and pin 4 is the output terminal of NOT gate circuit; the high level Vcc is connected with pin 5 of the control circuit, and pin 3 of the control circuit is grounded; the pin 1 and 2 are connected with the scanning signal and the field sync signal respectively, and resistor R1 is connected with the field sync signal and is grounded. The solution system, compared with the existing scan heads on the market, can completely solve the local overexposure problem of the aiming beam, hugely improve the decoding accuracy, stability, identification rate, decoding speed and power consumption of the scan head hugely, and realize cost-effectiveness easily.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: December 17, 2019
    Inventors: Dongsheng Wang, Hao Chen, Jiangtao Wei, Zhenhua Deng
  • Patent number: 10510386
    Abstract: A dynamic bit-line clamping circuit for computing-in-memory applications is configured to clamp a bit line via at least one reference signal and includes a clamping node, a first clamping unit, a second clamping unit, a first feedback controlling unit and a second feedback controlling unit. The first clamping unit is electrically connected between the bit line and the clamping node. The second clamping unit is electrically connected between the clamping node and a power source voltage and includes a switch. The second feedback controlling unit is electrically connected to the clamping node and the switch. The second feedback controlling unit generates a switching signal according to the at least one reference signal and a voltage level of the clamping node. The switch is switched by the switching signal so as to clamp the voltage level of the clamping node according to the at least one reference signal.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: December 17, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Wei-Hao Chen, Wei-Yu Lin