Abstract: A method for sampling coordinates of a touched point on a touch panel, includes the steps of: (a1) detecting a touched point at a low detection frequency to obtain two touch coordinates sequentially in time series; (a2) calculating a distance between the two touch coordinates; (a3) determining whether the distance between the two touch coordinates is greater than a first threshold distance; (a4) detecting a touched point at a high detection frequency to obtain a subsequent touch coordinate in time series; (a5) calculating a distance between two touch coordinates sequentially in time series at the high detection frequency; (a6) determining whether the distance obtained in the step (a5) is less than a second threshold distance; and (a7) detecting a touched point on the touch panel at the low detection frequency when the distance is less than the second threshold distance in the step (a6).

Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.

Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

Abstract: A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure. The raised source/drain region includes a top surface above a surface of the substrate by a distance. The interconnect plug connects to the raised source/drain region. The interconnect plug includes a doped region contacting the top surface of the raised source/drain region, a metal silicide region located on the doped region, and a metal region located on the metal silicide region.

Abstract: A three-dimensional integrated circuit (3DIC) and wireless information access methods thereof are provided. The proposed 3DIC includes a semiconductor structure, and a wireless power device (WPD) formed on the semiconductor structure for wirelessly receiving a power for operating a function selected from a group consisting of probing the semiconductor structure, testing the semiconductor structure and accessing a first information from the semiconductor structure.

Abstract: A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.

Abstract: A fan-out wafer comprises a first IC die having at least a first boundary scan cell (BSC) and a second BSC. The first BSC is coupled to a first demultiplexer. The second BSC is coupled to a first pad. A second IC die has at least a third BSC coupled to a second demultiplexer, and a second pad connected to the first pad. A first master path connects the first demultiplexer to the second demultiplexer. A first slave path connects the first demultiplexer to the second demultiplexer. The first pad and second pad are located between the first master path and the first slave path.

Abstract: A liquid crystal panel includes a TFT (Thin Film Transistor) substrate, a CF (Color Filter) substrate and liquid crystal layer arranged between the TFT substrate and the CF substrate. The liquid crystal panel includes a display area and a non-display area, the non-display area surrounds the display area, a sealing material coating area is arranged in the non-display area, and a sealing material is arranged in the sealing material coating area to seal the liquid crystal layer between the TFT substrate and the CF substrate. A first black matrix is arranged inside the CF substrate in the non-display area, devices including a metal layer are arranged inside the TFT substrate in the non-display area, and voids are arranged in the first black matrix of the CF substrate corresponding to at least a part of the devices including the metal layer.

Abstract: In some embodiments, in a method performed by at least one processor, a cell is characterized, by the at least one processor, with respect to an input transition characteristic considering different circuit topologies of a pre-driver driving the cell resulting in the same input transition characteristic.

Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.

Abstract: An exemplary liquid crystal display (LCD) includes a casing and a liquid crystal panel accommodated in the casing. The casing includes a frame and a window surrounded by an inner side of the frame. The liquid crystal panel includes an outside surface essentially serving as a display screen for displaying images and a peripheral wall. The liquid crystal panel is attached to the frame, with the inner side of the frame contacting the peripheral wall of the liquid crystal panel, and the display screen exposed outside of the casing.

Abstract: An exemplary liquid crystal display (LCD) includes a casing and a liquid crystal panel accommodated in the casing. The casing includes a frame and a window surrounded by an inner side of the frame. The liquid crystal panel includes an outside surface essentially serving as a display screen for displaying images and a peripheral wall. The liquid crystal panel is attached to the frame, with the inner side of the frame contacting the peripheral wall of the liquid crystal panel, and the display screen exposed outside of the casing.

Abstract: A display apparatus is disclosed. First and second conduction terminals are respectively arranged on inner sides of upper and lower substrates. The first and second conduction terminals are electrically connected, and first conduction terminals are respectively electrically connected with first signal traveling lines. In addition, second conduction terminals are respectively electrically connected with second signal traveling lines on the inner side of the lower substrate and pairs of alternative conduction terminals. First and second alternative conduction terminals are respectively arranged on the inner sides of the upper and lower substrates. Furthermore, the first and second alternative conduction terminals are respectively electrically connected through first repair lines, which are arranged on the inner side of the upper substrate. In addition, the first and second alternative conduction terminals are respectively electrically connected with the first repair lines and with alternative wires.

Abstract: A device for testing a bottom package of an integrated fan-out (InFO) Package-on-Package (PoP) comprises a bottom fixture having a space to accommodate the bottom package during testing and a detachable top cover, configured for conducting at least one test of the bottom package, wherein one or both of the bottom fixture and the top cover have a plurality of probing contacts for testing of the bottom package and wherein the device can be opened for placement of the bottom package under testing, and the cover is attachable to the bottom fixture for conducting the testing.

Abstract: A described method includes providing a semiconductor substrate. A first gate structure is formed on the semiconductor substrate and a sacrificial gate structure formed adjacent the first gate structure. The sacrificial gate structure may be used to form a metal gate structure using a replacement gate methodology. A dielectric layer is formed overlying the first gate structure and the sacrificial gate structure. The dielectric layer has a first thickness above a top surface of the first gate structure and a second thickness, less than the first thickness, above a top surface of the sacrificial gate structure. (See, e.g., FIGS. 5, 15, 26). Thus, a subsequent planarization process of the dielectric layer may not contact the first gate structure.

Abstract: A heterogeneous energy supply system includes an electric power management unit controlled by a control unit to output electric power. An electricity supply unit is powered by the electric power management unit, and is controlled by the control unit to regulate the electric power so as to provide an electricity output. An air supply unit is powered by the electric power management unit, and is controlled by the control unit to generate an air output. A hydrogen supply unit is powered by the electric power management unit, and is controlled by the control unit to generate a hydrogen gas output.

Abstract: A magnetic force generating device is provided for application to a first object that is movable relative to a second object providing a first magnetic force, and includes a coil disposed on the first object, a sensing module disposed on the first object adjacent to the coil for sensing a distance between the first and second objects, and a processor. When the sensed distance is shorter than a threshold value, the processor enables provision to the coil of a driving current having a magnitude negatively correlated to the sensed distance, so that the coil generates a second magnetic force, which is repulsive to the first magnetic force, in response to the driving current.

Abstract: A method of wire routing is provided. The method comprises obtaining data of cell layouts, generating a first database for the cell layouts, identifying, for each cell in the first database, whether the cell and another cell in the first database are routable in a pin layer, and generating a second database for routable cells.