Abstract: Disclosed is a wire clamp, comprising: a clamp body; a pair of arms coupled to the clamp body; and a piezoelectric actuator having a longitudinal axis extending between a first end and a second end, the actuator being coupled to the pair of arms at the first end and to the clamp body at the second end. The second end of the actuator is coupled to the clamp body by a preload mechanism for applying a preload force along the longitudinal axis, and the preload mechanism comprises at least one wedge having an inclined surface which is slidable over a mating inclined surface. Also disclosed is a method of applying a preload force to a piezoelectric actuator of a wire clamp, as well as a jig for applying a preload force to a piezoelectric actuator of a wire clamp.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. The semiconductor device also includes an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion. Each of the end portions has a first gate length longer than a second gate length of the intermediate portion and is located over the isolation structure.

Abstract: A wafer probing system includes a plurality of contacting pins connected to a test head. The system further includes a probe card electrically connectable with the test head, where the probe card includes a circuit board having a plurality of contact pads on opposite sides of the circuit board.

Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.

Abstract: A low-cost ESD protection device for high-voltage open-drain pad is disclosed, which has a first high-voltage (HV) NMOSFET coupled to a high-voltage (HV) open drain pad, a ground pad, a HV block unit and an ESD clamp unit and a low-voltage (LV) bias unit coupled to the first HV NMOSFET, a low-voltage (LV) trigger, the ESD clamp unit and the ground pad. The LV trigger is coupled to the HV block unit. The HV block unit blocks a high voltage from the HV open drain pad diode during normal operation and generates a trigger signal to the LV trigger when an ESD event is applied to the HV open drain pad. Then, the LV trigger turns on the ESD clamp unit to discharge an ESD current and switches the LV bias unit to turn off the first HV NMOSFET.

Abstract: A wafer packaging method includes the following steps. A light transmissive carrier is provided. A hydrolytic temporary bonding layer is formed on the light transmissive carrier. A first surface of a light transmissive protection sheet is bonded to the hydrolytic temporary bonding layer, such that the hydrolytic temporary bonding layer is located between the light transmissive protection sheet and the light transmissive carrier. A second surface of the light transmissive protection sheet facing away from the first surface is bonded to a third surface of a wafer. The light transmissive carrier, the hydrolytic temporary bonding layer, the light transmissive protection sheet, and the wafer are immersed in a high temperature liquid, such that adhesion force of the hydrolytic temporary bonding layer is eliminated. The light transmissive protection sheet and the wafer are obtained from the high temperature liquid.

Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

Abstract: A transport vehicle includes a driving unit, a wheel and a charging system. The charging system includes an electricity-generating tire and a converting unit. The electricity-generating tire has a tire body mounted on the wheel, and a piezoelectricity generating unit disposed at the tire body and configured to output electricity when the piezoelectricity generating unit is subjected to mechanical forces attributed to movement of the tire body on a ground surface. The converting unit operates to convert the electricity outputted by the piezoelectricity generating unit into a form of energy for storage in an energy storing unit.

Abstract: A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.

Abstract: A method and associated systems for analyzing a change request of a project that involves an IT system, where IT system contains IT artifacts that have predefined relationships. One or more processors obtain a change request; use information contained in the change request to select an applicable decomposition agent; use information in the selected decomposition agent to decompose the change request into a set of component sub-change requests; correlate at least one of the sub-change requests with one of the IT artifacts; and display the sub-change requests. In alternate implementations, selecting the applicable decomposition agent may require additional user input.

Abstract: The invention discloses an image processing method and an imager processing apparatus using the same. The method includes the following steps: receiving an training image; finding a minimum difference among the differences; determining whether the minimum difference is larger than a first threshold; if no, generating a first output value according to the first pixel, the background candidates and a plurality of weightings corresponding to the background candidates; updating a first background candidate corresponding to the minimum difference; updating a first weighting related to the first background candidate; if yes, adding the first pixel as a new background candidate to the background candidates and adding a new weighting corresponding to the new background candidate to the weightings; and detecting whether a moving object existing in an incoming image according to the background candidates and the weightings.

Abstract: Among other things, one or more techniques or systems for evaluating a tiered semiconductor structure, such as a stacked CMOS structure, for misalignment are provided. In an embodiment, a connectivity test is performed on vias between a first layer and a second layer to determine a via diameter and a via offset that are used to evaluate misalignment. In an embodiment, a connectivity test for vias within a first layer is performed to determine an alignment rotation based upon which vias are connected through a conductive arc within a second layer or which vias are connected to a conductive pattern out of a set of conductive patterns. In this way, the via diameter, the via offset, or the alignment rotation are used to evaluate the tiered semiconductor structure, such as during a stacked CMOS process, for misalignment.

Abstract: An encapsulant composition is provided, including at least one resin monomer, a filler and a photoinitiator, wherein the at least one resin monomer is selected from the group consisting of acrylic resin monomer, epoxy resin monomer, silicone resin monomer and compositions thereof, and the filler is of about 0.1˜15 weight % of the encapsulant composition. A method for forming encapsulant materials is also provided.

Abstract: A low voltage bandgap reference circuit includes a positive temperature coefficient circuit unit, a negative temperature coefficient circuit unit and a load unit, wherein the positive temperature coefficient circuit unit comprises a first differential operational amplifier, a first, second and third transistor, a first resistor, a first and second diode, and the negative temperature coefficient circuit unit includes a second differential operational amplifier, a fourth, fifth and sixth transistor, a second resistor and a third diode. The low voltage bandgap reference circuit provides a current having a positive temperature coefficient characteristics and a current having a negative temperature coefficient characteristics to flow through the load in order to generate a stable reference voltage less affected by the temperature. Therefore, it avoids the problems of the low voltage bandgap reference circuit that can not be activated at low voltage.

Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.

Abstract: Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer.

Abstract: A pneumatic driving module is for mounting on and driving a vehicle. The vehicle includes at least one wheel that includes a rim. The pneumatic driving module includes a storage tank, an air delivery unit and an air-driving mechanism. The storage tank is for storing compressed air therein. The air delivery unit includes a tube fluidly communicating with the storage tank for discharging the compressed air stored in the storage tank. The air-driving mechanism fluidly communicates with the tube, and is configured to be mounted directly to the wheel for providing dynamic energy associated with the compressed air to the rim to drive rotation of the wheel.

Abstract: A light-emitting diode includes a substrate, the substrate including an upper surface, a bottom surface opposite to the upper surface, and a side surface; a first type semiconductor layer on the upper surface, wherein the first type semiconductor layer includes a first portion and a second portion, and the second portion includes an edge surrounding the first portion; a light-emitting layer on the first portion; and a second type semiconductor layer on the light-emitting layer, wherein the second portion includes a first surface and a second surface, and a first distance is between the first surface and the upper surface, and a second distance is between the second surface and the upper surface and is smaller than the first distance; wherein the first surface is rougher than the second surface, and the second surface is located at the edge.

Abstract: The present invention provides a touch panel and a touch display device, the touch panel includes: a transparent substrate; a conductive layer disposed on the transparent substrate, where the conductive layer includes a plurality of first conductive patterns and a plurality of second conductive patterns intersecting with the plurality of first conductive patterns, and each of the second conductive patterns is separated into multiple segments by the plurality of first conductive patterns; a color resistance insulating layer disposed on the conductive layer, where the color resistance insulating layer includes a plurality of through-holes; and a metal bridging layer disposed on the color resistance insulating layer, where the multiple segments of the second conductive pattern are connected together by the metal bridging layer via the through-holes.

Abstract: Embodiments of the present disclosure provide a sequence synchronization apparatus and method and a receiver. The sequence synchronization apparatus includes: a signal receiving unit configured to receive a clock synchronized signal including a training symbol, the training symbol being in-phase modulated or being modulated with a fixed phase difference based on all or part of subcarriers; and a symbol detecting unit configured to detect the training symbol, so as to achieve sequence synchronization of the signal. With the embodiments of the present disclosure, not only sequence synchronization may be achieved by using minimum complexity as possible, but also the sequence synchronization apparatus is made simple, fast and accurate.