Abstract: A device includes a substrate, a dielectric structure, a gate electrode, and a drain electrode. The dielectric structure is over the substrate. The dielectric structure includes a first portion, a second portion, and a third portion. The first portion has a first equivalent oxide thickness. The second portion is spaced apart from the first portion and has a second equivalent oxide thickness. The third portion laterally surrounds the first and second portions and has a third equivalent oxide thickness greater than the first equivalent oxide thickness of the first portion. The gate electrode is over the dielectric structure and in contact with the first and third portions of the dielectric structure. The drain electrode is over the dielectric structure and in contact with the second and third portions of the dielectric structure.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a sensor semiconductor layer. The sensor semiconductor layer is doped with a first dopant. A photodetector is along a frontside of the sensor semiconductor layer. A backside semiconductor layer is along a backside of the sensor semiconductor layer, opposite the frontside. The backside semiconductor layer is doped with a second dopant. A diffusion barrier structure is between the sensor semiconductor layer and the backside semiconductor layer. The diffusion barrier structure includes a third dopant different from the first dopant and the second dopant.

Abstract: A high electron mobility transistor includes: a first semiconductor layer over a substrate, and a second semiconductor layer over the first semiconductor layer, the second semiconductor layer having a band gap discontinuity with the first semiconductor layer, and at the first semiconductor layer and/or the second conductive layer includes indium. A top layer is over the second semiconductor layer, and a metal layer is over, and extends into, the top layer, the top layer separating the metal layer from the second semiconductor layer. A gate electrode is over the top layer, a third semiconductor layer being between the gate electrode and the top layer, where a sidewall of the third semiconductor layer and a sidewall of the metal layer are separated. A source and drain are on opposite sides of the gate electrode, the top layer extending continuously from below the source, below the gate electrode, and below the drain.

Abstract: A memory device includes a transistor and a memory cell. The memory cell includes a bottom electrode, a top electrode, and a dielectric structure. The top electrode is electrically connected to the transistor. The dielectric structure includes a thin portion and a thick portion. The thin portion is sandwiched between the bottom electrode and the top electrode. The thick portion is thicker than the thin portion and between the bottom electrode and the top electrode.

Abstract: Provided herein are compositions that include a single nucleic acid vector or two different nucleic acid vectors, and the use of these compositions to treat hearing loss in a subject.

Abstract: A parabolic reflector device (also referred to herein as a parabolic lens device) is disclosed which includes a plurality of parabolic lens members and a mirror member which couple together and collectively provide a light-transmissive structure for multiplexing or demultiplexing of an optical signal. The parabolic reflector device can be implemented within optical subassembly modules to support operations of transmitter optical subassemblies (TOSAs) and/or receiver optical subassemblies (ROSAs).

Abstract: A masking circuit of a content addressable memory (CAM) includes a masking control circuit and a level control circuit. The masking control circuit generates a masking signal according to a word line (WL) signal and a write enablement (WE) signal. When both the WL and WE signals are at a first level, the masking signal is a first masking signal; when they are at different levels respectively, the masking signal is a second masking signal. The level control circuit generates a level control signal according to the masking signal for determining whether to pull a voltage level of a match line of the CAM to a predetermined level. When the masking signal is the first masking signal, the level control circuit pulls the voltage level to the predetermined level; and when the masking signal is the second masking signal, the level control circuit does not interfere in the voltage level.

Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

Abstract: A semiconductor device includes a P-doped well having a first concentration of P-type dopants in the substrate; a P-doped region having a second concentration of P-type dopants in the substrate and extending around a perimeter of the P-doped well; a shallow trench isolation structure (STI) between the P-doped well and the P-doped region; an active area on the substrate, the active area including an emitter region and a collector region; a deep trench isolation structure (DTI) extending through the active area and between the emitter region and the collector region; and an electrical connection between the emitter region and the P-doped region.

Abstract: An optical fiber holder is disclosed herein that includes at least one confinement slot for routing intermediate optical fibers within a housing of an optical assembly module, and preferably, a plurality of confinement slots for maintaining a target/nominal fiber bending radius for one or more intermediate optical fibers within the housing. Preferably, the optical fiber holder is disposed within the housing of an optical subassembly between an optical component, e.g., a TOSA arrangement and/or ROSA arrangement, and optical coupling receptacles, e.g., LC coupling receptacles, for optically coupling with external fibers for sending and/or receiving optical signals.

Abstract: A method of making a Fin Field-effect transistor includes: providing a substrate and a plurality of fin structures on a surface of the substrate; forming a shallow trench isolation structure between the plurality of fin structures; forming a stress layer on a side of the shallow trench isolation structure away from the substrate; heat treating the stress layer and the plurality of fin structures; and removing the stress layer. The fin structures are spaced apart from each other. The stress layer covers a part of the fin structures away from the substrate.

Abstract: The present disclosure is generally directed to a component bridge that couples to a feedthrough device to provide additional component mounting surface area within a TOSA housing, and preferably, within a hermetically-sealed TOSA housing. The component bridge includes a body that defines a component mounting surface to couple to electrical components, e.g., one or more filtering capacitors, and a notched portion to provide an accommodation groove. The component bridge includes at least one projection/leg for coupling to a mounting surface of a feedthrough device. The accommodation groove of the component bridge allows for other electrical components, e.g., RF traces, to be patterned/disposed on to the mounting surface and extend at least partially through the accommodation groove while remaining electrically isolated from the same. Accordingly, the component bridge further increases available component mounting surface area for existing feedthrough devices without necessity of re-design and/or modification.

Abstract: A touch panel includes a substrate, touch signal lines, sub-pixels, touch electrode groups, and at least one common signal array. The touch signal lines and the sub-pixels are located on substrate. Each of the sub-pixels includes a switch element and a pixel electrode. The switch element is electrically connected to a corresponding scan line and a corresponding data line. The touch electrode groups include touch electrodes. The touch electrodes overlap the pixel electrodes of the sub-pixels. Each of the touch electrode groups is electrically connected to a corresponding one of the touch signal lines. The common signal array includes common electrodes. Each of the common electrodes overlaps at least one of the scan line and the data line. The number of the sub-pixels overlapped by the common signal array is greater than the number of the sub-pixels overlapped by each of the touch electrode groups.

Abstract: A voltage balance circuit includes a battery module connected to an external power source, a voltage dividing module, a detection module and a control module. The battery module includes a plurality of batteries connected in series. The voltage dividing module includes a plurality of bleeder resistors. Each bleeder resistor is connected with one battery in parallel. The detection module includes a plurality of thermistors, fixation resistances and micro-controllers. Each thermistor is arranged beside one bleeder resistor. Each thermistor is connected with one fixation resistance in series. Each micro-controller is connected with one thermistor and the one fixation resistance. The control module includes a plurality of switches and an analog front end component. Each switch is connected with the one bleeder resistor in series. Each switch is connected to the analog front end component, and the analog front end component is connected to the one micro-controller.

Abstract: The present disclosure is generally directed to an optical demultiplexer for use in an optical transceiver module having a truncated profile/shape to increase tolerance and accommodate adjacent optical components. In more detail, the optical demultiplexer comprises a body with at least one truncated corner at the input end. The at least one truncated corner allows the optical demultiplexer to be disposed/mounted, e.g., directly, on a densely populated transceiver substrate, e.g., a printed circuit board (PBC), and provide additional tolerance/space for mounting of circuitry and/or components within the region that would normally be occupied by corner(s) of the optical demultiplexer body. The at least one truncated corner may be introduced in a post-production step, e.g., via cut & polishing, or introduced during formation of the optical demultiplexer using, for instance, photolithography techniques.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

Abstract: A memory device includes a controller circuit, a first stage circuit, and a second stage circuit. The controller circuit outputs a first global pre-charge control signal, a second global pre-charge control signal, and a first local pre-charge control signal. The first stage circuit pre-charges a first global match line according to the first global pre-charge control signal, and to compare search data with first data, in order to determine whether to adjust a first level of the first global match line. The second stage circuit selectively pre-charges a second global match line according to the first level and the second global pre-charge control signal, and determines whether to compare the search data with second data according to a second level of the second global match line and the first local pre-charge control signal, in order to adjust the second level.

Abstract: A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.