Abstract: Provided is a method for synthesizing a perovskite quantum dot film, including: preparing a cellulose nanocrystal (CNC) solution, wherein the CNC solution includes a plurality of CNCs with sulfate groups; preparing a precursor solution; mixing the CNC solution and the precursor solution to form a mixed solution; and filtering and drying the mixed solution to form a perovskite quantum dot film.

Abstract: A memory scheduler in a hypervisor allocates physical memory to virtual machines (VMs) based on memory usages metrics generated within the VMs and provided to the hypervisor. More particularly, the memory scheduler determines an allocation target for each VM based on a guest-generated memory usage metric associated with the VM. The allocation target can be increased or decreased from its previous value to reflect changing needs in the VM. Physical memory is allocated when a VM requests it, and is reclaimed during a reclamation process based on its associated allocation target.

Abstract: In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

Abstract: The present invention pertains to anti-coronaviral compounds. The disclosure includes a method for preventing and/or treating a coronavirus infection through the inhibition of a cysteine protease in a virus, particularly SARS-COV-2. Also provided includes the composition/pharmaceutical composition for preventing and/or treating a coronavirus infection comprising any of the compounds, pharmaceutically acceptable salt thereof, or its mixture, and the use of the compounds.

Abstract: A multi-processor system includes multiple processors arranged in multiple clusters. Different clusters have different power and performance characteristics. The system includes a task scheduler to schedule tasks to the processors. The task scheduler, in response to detection of a scheduling event trigger, is operative to identify a scheduling objective between a first objective of energy optimization and a second objective of load balance. The scheduling objective is identified based on at least respective operating frequencies and loading of all processors in a highest-capacity cluster of the multiple clusters. According to the identified scheduling objective, the task scheduler schedules a given task to a processor selected among the processors in the multiple clusters.

Abstract: A touch panel includes a substrate, touch signal lines, sub-pixels, touch electrode groups, and at least one common signal array. The touch signal lines and the sub-pixels are located on substrate. Each of the sub-pixels includes a switch element and a pixel electrode. The switch element is electrically connected to a corresponding scan line and a corresponding data line. The touch electrode groups include touch electrodes. The touch electrodes overlap the pixel electrodes of the sub-pixels. Each of the touch electrode groups is electrically connected to a corresponding one of the touch signal lines. The common signal array includes common electrodes. Each of the common electrodes overlaps at least one of the scan line and the data line. The number of the sub-pixels overlapped by the common signal array is greater than the number of the sub-pixels overlapped by each of the touch electrode groups.

Abstract: The present disclosure is generally directed to a component bridge that couples to a feedthrough device to provide additional component mounting surface area within a TOSA housing, and preferably, within a hermetically-sealed TOSA housing. The component bridge includes a body that defines a component mounting surface to couple to electrical components, e.g., one or more filtering capacitors, and a notched portion to provide an accommodation groove. The component bridge includes at least one projection/leg for coupling to a mounting surface of a feedthrough device. The accommodation groove of the component bridge allows for other electrical components, e.g., RF traces, to be patterned/disposed on to the mounting surface and extend at least partially through the accommodation groove while remaining electrically isolated from the same. Accordingly, the component bridge further increases available component mounting surface area for existing feedthrough devices without necessity of re-design and/or modification.

Abstract: The present disclosure is generally directed to a monitor photodiode (MPD) submount for use in optical transceivers that includes a body with a conductive trace pattern disposed on multiple surfaces of the same to allow for vertical mounting of an associated MPD and simplified electrical interconnection with TOSA circuitry without the necessity of electrical interconnection. The MPD submount includes a body defined by a plurality of sidewalls. At least one surface of the body provides a mounting surface for coupling to and supporting an MPD. The MPD submount further includes a conductive trace pattern that provides at least one conductive path that is disposed on the mounting surface and on at least one adjoining sidewall. The portion of the at least one conductive path disposed on the adjoining sidewall extends substantially transverse relative to the surface defining the transceiver/transmitter substrate when the MPD submount is coupled to the same.

Abstract: The present disclosure is generally directed to a monitor photodiode (MPD) submount for use in optical transceivers that includes a body with a conductive trace pattern disposed on multiple surfaces of the same to allow for vertical mounting of an associated MPD and simplified electrical interconnection with TOSA circuitry without the necessity of electrical interconnection. The MPD submount includes a body defined by a plurality of sidewalls. At least one surface of the body provides a mounting surface for coupling to and supporting an MPD. The MPD submount further includes a conductive trace pattern that provides at least one conductive path that is disposed on the mounting surface and on at least one adjoining sidewall. The portion of the at least one conductive path disposed on the adjoining sidewall extends substantially transverse relative to the surface defining the transceiver/transmitter substrate when the MPD submount is coupled to the same.

Abstract: The present disclosure is generally directed to a housing for use with optical transceivers or transmitters that includes integrated heatsinks with a graphene coating to increase thermal dissipation during operation. In more detail, an embodiment of the present disclosures includes a housing that defines at least first and second sidewalls and a cavity disposed therebetween. The first and/or second sidewalls can include integrated heatsinks to dissipate heat generated by optical components, e.g., laser diodes, laser diode drivers, within the cavity of the housing. The integrated heatsinks can include at least one layer of graphene disposed thereon to increase thermal performance, and in particular, to decrease thermal resistance of the heatsink and promote heat dissipation.

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: Provided is a method for synthesizing a perovskite quantum dot film, including: preparing a cellulose nanocrystal (CNC) solution, wherein the CNC solution includes a plurality of CNCs with sulfate groups; preparing a precursor solution; mixing the CNC solution and the precursor solution to form a mixed solution; and filtering and drying the mixed solution to form a perovskite quantum dot film.

Abstract: The present disclosure is generally directed to a housing for use with optical transceivers or transmitters that includes integrated heatsinks with a graphene coating to increase thermal dissipation during operation. In more detail, an embodiment of the present disclosures includes a housing that defines at least first and second sidewalls and a cavity disposed therebetween. The first and/or second sidewalls can include integrated heatsinks to dissipate heat generated by optical components, e.g., laser diodes, laser diode drivers, within the cavity of the housing. The integrated heatsinks can include at least one layer of graphene disposed thereon to increase thermal performance, and in particular, to decrease thermal resistance of the heatsink and promote heat dissipation.

Abstract: The present disclosure is generally directed to an optical demultiplexer for use in an optical transceiver module having a truncated profile/shape to increase tolerance and accommodate adjacent optical components. In more detail, the optical demultiplexer comprises a body with at least one truncated corner at the input end. The at least one truncated corner allows the optical demultiplexer to be disposed/mounted, e.g., directly, on a densely populated transceiver substrate, e.g., a printed circuit board (PBC), and provide additional tolerance/space for mounting of circuitry and/or components within the region that would normally be occupied by corner(s) of the optical demultiplexer body. The at least one truncated corner may be introduced in a post-production step, e.g., via cut & polishing, or introduced during formation of the optical demultiplexer using, for instance, photolithography techniques.

Abstract: The present invention relates to a forgery detection system and its method for biomedical experiment images, especially for molecular-biological experiment images, such as western blot (WB) and polymerase chain reaction (PCR) results. The forgery detection system mainly comprises a processing module, an image difference computing module, a thresholding module, and an image mixing module are formed in an image analyzing device in the form of a library, a variable or an operand. Moreover, the processing module has a quantization parameter establishing unit, a similar computing unit, and a pseudo background generating unit. The purpose of the image analyzing device is to display an artificial image on the input image.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region having a first doping type disposed in a semiconductor substrate. A second doped region having a second doping type different than the first doping type is disposed in the semiconductor substrate and laterally spaced from the first doped region. A waveguide structure is disposed in the semiconductor substrate and laterally between the first doped region and the second doped region. A photodetector is disposed at least partially in the semiconductor substrate and laterally between the first doped region and the second doped region. The waveguide structure is configured to guide one or more photons into the photodetector. The photodetector has an upper surface that continuously arcs between opposite sidewalls of the photodetector. The photodetector has a lower surface that continuously arcs between the opposite sidewalls of the photodetector.

Abstract: The present disclosure, in some embodiments, relates to a transistor device. The transistor device includes a layer of GaN over a substrate. A mobility-enhancing layer of AlzGa(1-z)N is over the layer of GaN and has a first molar fraction z in a first range of between approximately 0.25 and approximately 0.4. A resistance-reducing layer of AlxGa(1-x)N is over the mobility-enhancing layer and has a second molar fraction x in a second range of between approximately 0.1 and approximately 0.15. A source has a source contact and an underlying source region. A drain has a drain contact and an underlying drain region. The source and drain regions extend through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N. The source and drain regions have bottoms over a bottom of the mobility-enhancing layer of AlzGa(1-z)N. A gate structure is laterally between the source and drain contacts.

Abstract: Nucleic acid aptamers capable of binding to lymphocyte activation gene 3 (LAG-3) and uses thereof for modulating immune responses. Such aptamers may comprise a G-rich motif, for example, GX1GGGX2GGTX3A (SEQ ID No: 1), in which each of X1 and X2 are independently G, C, or absent, and X3 is T or C, or L-(G)n-L?, in which n is an integer of 5-9 inclusive, and L and L? are nucleotide segments having complementary sequences. Also provided herein are multimeric nucleic acid aptamers containing a backbone moiety, which comprises a palindromic sequence.

Abstract: A memory device includes a controller circuit, a first stage circuit, and a second stage circuit. The controller circuit outputs a first global pre-charge control signal, a second global pre-charge control signal, and a first local pre-charge control signal. The first stage circuit pre-charges a first global match line according to the first global pre-charge control signal, and to compare search data with first data, in order to determine whether to adjust a first level of the first global match line. The second stage circuit selectively pre-charges a second global match line according to the first level and the second global pre-charge control signal, and determines whether to compare the search data with second data according to a second level of the second global match line and the first local pre-charge control signal, in order to adjust the second level.

Abstract: Method for manufacturing terephthalic acid includes following steps: providing a titrant receptor solution, the titrant receptor solution being water; adding disodium terephthalate aqueous solution and an acid titrant into the titrant receptor solution to form terephthalic acid crystals and an end-point solution, and separating the terephthalic acid crystals from the end-point solution.