Abstract: A modular pneumatic somatosensory device comprises a main body, a plurality of airbags, a plurality of inflating modules and a control module. The airbags are detachably disposed at different positions of the main body, and at least a part of the airbags have different sizes. The inflating modules are detachably disposed on the main body, and each inflating module is correspondingly connected with at least one of the airbags. The control module is detachably disposed on the main body and is electrically connected with the inflating modules. The control module controls the inflating modules to inflate the corresponding airbags according to a control signal.

Abstract: The present disclosure relates to a leveling control method, device and system, a motor grader. The leveling control method includes: acquiring elevations of a current position of a blade of a motor grader and a target position, and a movement speed of the motor grader, wherein the target position is on the ground with a certain horizontal distance from the current position along a movement direction of the motor grader; determining a movement time of the blade from the current position to the target position from the horizontal distance and the movement speed; determining a lifting speed of a lifting cylinder from an elevation difference between the elevation of the target position and the elevation of the current position and the movement time; and controlling the lifting cylinder to adjust the blade to move from the current position to the target position according to the lifting speed.

Abstract: An embedded circuit board, made without gas bubbles or significant internal gaps according to a manufacturing method which is provided, includes an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces and a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.

Abstract: A projection device including a casing, a light source module, an optical engine module and a projection lens is provided. A front cover, a rear cover, a first side cover, a second side cover, an upper cover and a lower cover of the casing surround an accommodating space. The light source module includes a first and a second light sources, and a first and a second light source heat dissipation modules. The lower cover has a first, a second and a third air inlets. The first and the second side covers respectively have a first and a second air outlets. The first and the second light source heat dissipation modules are correspondingly disposed above the first air inlet and correspond to the first air outlet. The second and the third air inlets are respectively disposed below two sides of the projection lens and adjacent to the front cover.

Abstract: A bonded assembly includes an interposer; a semiconductor die that is attached to the interposer and including a planar horizontal bottom surface and a contoured sidewall; a high bandwidth memory (HBM) die that is attached to the interposer; and a dielectric material portion contacting the semiconductor die and the interposer. The contoured sidewall includes a vertical sidewall segment and a non-horizontal, non-vertical surface segment that is adjoined to a bottom edge of the vertical sidewall segment and is adjoined to an edge of the planar horizontal bottom surface of the semiconductor die. The vertical sidewall segment and the non-horizontal, non-vertical surface segment are in contact with the dielectric material portion. The contoured sidewall may provide a variable lateral spacing from the HBM die to reduce local stress in a portion of the HBM die that is proximal to the interposer.

Abstract: Semiconductor structures and methods are provided. An exemplary method includes depositing a first conductive material layer over a substrate, patterning the first conductive material layer to form a first conductor plate over the substrate, forming a first high-K dielectric layer over the first conductor plate, forming a second high-K dielectric layer on the first high-K dielectric layer, forming a third high-K dielectric layer on the second high-K dielectric layer, and forming a second conductor plate over the third high-K dielectric layer and vertically overlapped with the first conductor plate, where a composition of the first high-K dielectric layer is the same as a composition of the third high-K dielectric layer and is different from a composition of the second high-K dielectric layer.

Abstract: A whole-vehicle-based method for evaluating extreme pressure and antiwear properties of grease includes injecting the grease onto a key bearing pin and causing the engineering machine to operate without load is disclosed. The method includes causing the engineering machine to operate under a load of 10% to 150% rated load at least once, viewing and analyzing a wear condition of a surface of the bearing pin, and issuing a whole-vehicle-based evaluation report of extreme pressure and antiwear properties of grease. The engineering machine is caused to operate once under a load of 10% to 150% rated load for 0.5 min to 100 h.

Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.

Abstract: A method includes forming a first capacitor electrode; forming a first oxygen-blocking layer on the first capacitor electrode; forming an capacitor insulator layer on the first oxygen-blocking layer; forming a second oxygen-blocking layer on the capacitor insulator layer; forming a second capacitor electrode on the second oxygen-blocking layer; and forming a first contact plug that is electrically coupled to the first capacitor electrode and a second contact plug that is electrically coupled to the second capacitor electrode.

Abstract: A method includes providing first and second channel layers in NMOS and PMOS regions respectively of a substrate; depositing a first layer comprising hafnium oxide over the first and second channel layers; forming a first dipole pattern over the second channel layer and not over the first channel layer; driving a first metal from the first dipole pattern into the first layer by annealing; removing the first dipole pattern; depositing a second layer comprising hafnium oxide over the first layer and over the first and second channel layers; forming a second dipole pattern over the second layer and the first channel layer and not over the second channel layer; driving a second metal from the second dipole pattern into the second layer by annealing; removing the second dipole pattern; and depositing a third layer comprising hafnium oxide over the second layer and over the first and the second channel layers.

Abstract: A method includes forming a capacitor, which includes forming a first capacitor electrode, forming a first capacitor insulator over the first capacitor electrode, and forming a second capacitor electrode over and contacting the first capacitor insulator. The formation of the first capacitor insulator includes oxidizing a top surface layer of the first capacitor electrode to form a metal oxide layer on the first capacitor electrode, depositing an aluminum oxide layer through a first ALD process having a first plurality of ALD cycles, with the first plurality of ALD cycles having a first ALD cycle number, and depositing a high-k dielectric layer over the aluminum oxide layer. The high-k dielectric layer is deposited through a second ALD process having a second ALD cycle number different from the first ALD cycle number.

Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.

Abstract: Structures of a semiconductor device structure are provided. The semiconductor device structure includes a first insulating layer formed over a semiconductor substrate and an interconnect structure formed in the first insulating layer. The semiconductor device structure also includes a second insulating layer formed over the first insulating layer and a capacitor device embedded in the second insulating layer. The capacitor device includes a first capacitor electrode layer electrically connected to the interconnect structure, a capacitor insulating stack formed over the first capacitor electrode layer and a second capacitor electrode layer formed over the capacitor insulating stack. The capacitor insulating stack includes first layers alternatingly stacked with second layers. The dielectric constant of the first layer is different than the dielectric constant of the second layer.

Abstract: A fixture for heat pressing process is applied to a hot pressing machine for hot pressing two elastic plastic pieces so as to manufacture an airbag. The two elastic plastic pieces are disposed between the fixture and the hot pressing machine. The fixture includes a first frame, a second frame and a flexible heat blocking layer. The first frame includes two first brackets, which are separated from each other with a first distance. The second frame includes two second brackets, which are separated from each other with a second distance, and located at two ends of the first brackets, respectively. The flexible heat blocking layer is fixed by the first frame and/or the second frame.

Abstract: A modular pneumatic somatosensory device comprises a main body, a plurality of airbags, a plurality of inflating modules and a control module. The airbags are detachably disposed at different positions of the main body, and at least a part of the airbags have different sizes. The inflating modules are detachably disposed on the main body, and each inflating module is correspondingly connected with at least one of the airbags. The control module is detachably disposed on the main body and is electrically connected with the inflating modules. The control module controls the inflating modules to inflate the corresponding airbags according to a control signal.

Abstract: In an embodiment, a device includes: a first gate dielectric on a first channel region of a first semiconductor feature; a first gate electrode on the first gate dielectric; a second gate dielectric on a second channel region of a second semiconductor feature, the second gate dielectric having a greater crystallinity than the first gate dielectric; and a second gate electrode on the second gate dielectric.

Abstract: A method includes depositing a first high-k dielectric layer over a first semiconductor region, performing a first annealing process on the first high-k dielectric layer, depositing a second high-k dielectric layer over the first high-k dielectric layer; and performing a second annealing process on the first high-k dielectric layer and the second high-k dielectric layer.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: Semiconductor devices and methods which utilize a passivation dopant to passivate a gate dielectric layer are provided. The passivation dopant is introduced to the gate dielectric layer through a work function layer using a process such as a soaking method. The passivation dopant is an atom which may help to passivate electrical trapping defects, such as fluorine.

Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.