Patents by Inventor Hao-Hsuan Chang
Hao-Hsuan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088307Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Publication number: 20240071981Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.Type: ApplicationFiled: November 1, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
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Publication number: 20230387994Abstract: A method includes receiving CSI frames among P CSI frames transmitted from another electronic device. The method includes estimating a CSI from each of the received CSI frames as an available CSI estimate. The method includes identifying an impairment model accounting for inclusion of amplitude or phase errors of an estimated CSI corresponding to a p-th CSI frame among the P CSI frames. The method includes compensating, via the impairment model, for the errors in amplitude and phase of P CSI estimates. Compensating for the errors in amplitude and phase of the P CSI estimates can be based on: approximating a missing CSI estimate based on the available CSI estimates; determining an AGC gain value; or computing the errors in the phase based on a weighted least-squares solution. The method includes estimating a breathing rate of a subject based on different spatial dimensions of the P compensated CSI estimates.Type: ApplicationFiled: May 22, 2023Publication date: November 30, 2023Inventors: Vishnu Vardhan Ratnam, Hao Chen, Abhishek Sehgal, Hao-Hsuan Chang
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Patent number: 11762293Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.Type: GrantFiled: May 11, 2021Date of Patent: September 19, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hao-Hsuan Chang, Da-Jun Lin, Yao-Hsien Chung, Ting-An Chien, Bin-Siang Tsai, Chih-Wei Chang, Shih-Wei Su, Hsu Ting, Sung-Yuan Tsai
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Publication number: 20230282740Abstract: A high electron mobility transistor including a substrate; a channel layer on the substrate; an electron supply layer on the channel layer; a dielectric passivation layer on the electron supply layer; a gate recess in the dielectric passivation layer and the electron supply layer; a surface modification layer on an interior surface of the gate recess; and a P-type GaN layer in the gate recess and on the surface modification layer. The surface modification layer has a gradient silicon concentration.Type: ApplicationFiled: May 9, 2023Publication date: September 7, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Chang, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Ting-An Chien, Bin-Siang Tsai
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Publication number: 20230238455Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.Type: ApplicationFiled: March 31, 2023Publication date: July 27, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Chang, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Ting-An Chien, Bin-Siang Tsai
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Patent number: 11688790Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.Type: GrantFiled: January 6, 2021Date of Patent: June 27, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Chang, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Da-Jun Lin, Ting-An Chien, Bin-Siang Tsai
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Patent number: 11688802Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is then subjected to an oxidation treatment or a nitridation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.Type: GrantFiled: February 18, 2021Date of Patent: June 27, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Chang, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Ting-An Chien, Bin-Siang Tsai
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Publication number: 20230145175Abstract: A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from that of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed on the gate.Type: ApplicationFiled: January 3, 2023Publication date: May 11, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Chang, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Da-Jun Lin, Ting-An Chien, Bin-Siang Tsai
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Publication number: 20230109149Abstract: A method includes receiving CSI data for at least one communication link between a first electronic device (ED1) and a Wi-Fi device in a 3D space. The method includes preprocessing the CSI data; and determining whether a motion of an object is detected within a threshold distance to the ED1 based on the preprocessed CSI data. The detection of the motion of the object corresponds to a determination that the object is present in the space. The detection of no motion of the object corresponds to a determination that the object is not present in the space. The method includes outputting at least one of: a first indicator indicating that the space is empty, in response to the determination that the object is not present in the space; or a second indicator indicating that the space is occupied, in response to the determination that the object is present in the space.Type: ApplicationFiled: September 29, 2022Publication date: April 6, 2023Inventors: Hao Chen, Guanbo Chen, Hao-Hsuan Chang, Dong Li, Abhishek Sehgal
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Publication number: 20230109057Abstract: A method includes obtaining Wi-Fi channel state information (CSI) data on a transmit antenna/receive antenna pair over a time period. The method also includes removing one or more anomalies present in the CSI data. The method also includes performing at least one of phase compensation and amplitude compensation on the CSI data to generate clean CSI data. The method also includes detecting a number of distinct respiration rates based on the clean CSI data. The method also includes, for each of the distinct respiration rates, determining a number of people that have that distinct respiration rate.Type: ApplicationFiled: September 28, 2022Publication date: April 6, 2023Inventors: Hao-Hsuan Chang, Hao Chen, Vishnu Vardhan Ratnam, Abhishek Sehgal, Jianzhong Zhang
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Publication number: 20220365433Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.Type: ApplicationFiled: May 11, 2021Publication date: November 17, 2022Inventors: Hao-Hsuan Chang, Da-Jun Lin, Yao-Hsien Chung, Ting-An Chien, Bin-Siang Tsai, Chih-Wei Chang, Shih-Wei Su, Hsu Ting, Sung-Yuan Tsai
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Publication number: 20220262939Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is then subjected to an oxidation treatment or a nitridation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.Type: ApplicationFiled: February 18, 2021Publication date: August 18, 2022Inventors: Chih-Wei Chang, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Ting-An Chien, Bin-Siang Tsai
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Publication number: 20220165866Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.Type: ApplicationFiled: January 6, 2021Publication date: May 26, 2022Inventors: Chih-Wei Chang, Yao-Hsien Chung, Shih-Wei Su, Hao-Hsuan Chang, Da-Jun Lin, Ting-An Chien, Bin-Siang Tsai
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Patent number: 11114331Abstract: A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.Type: GrantFiled: June 4, 2019Date of Patent: September 7, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hao-Hsuan Chang, Hung-Chun Lee, Shu-Ming Yeh, Ting-An Chien, Bin-Siang Tsai
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Publication number: 20210273089Abstract: A semiconductor device includes a substrate having at least two fins thereon and an isolation trench between the at least two fins; and an isolation structure in the isolation trench. The isolation structure consists of a liner layer covering a lower sidewall of each of the at least two fins and a bottom surface of the isolation trench, and a stress-buffer film on the liner layer. The stress-buffer film is a silicon suboxide film of formula SiOy, wherein y<2.Type: ApplicationFiled: May 17, 2021Publication date: September 2, 2021Inventors: Shih-Wei Su, Hao-Hsuan Chang, Chih-Wei Chang, Chi-Hsuan Cheng, Ting-An Chien, Bin-Siang Tsai
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Patent number: 11043596Abstract: A method for forming a semiconductor device is disclosed. A substrate having at least two fins thereon and an isolation trench between the at least two fins is provided. A liner layer is then deposited on the substrate. The liner layer conformally covers the two fins and interior surface of the isolation trench. A stress-buffer film is then deposited on the liner layer. The stress-buffer film completely fills a lower portion that is located at least below half of a trench depth of the isolation trench. A trench-fill oxide layer is then deposited to completely fill an upper portion of the isolation trench.Type: GrantFiled: June 25, 2019Date of Patent: June 22, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Wei Su, Hao-Hsuan Chang, Chih-Wei Chang, Chi-Hsuan Cheng, Ting-An Chien, Bin-Siang Tsai
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Patent number: 11037833Abstract: A method for forming a semiconductor device is provided. A dielectric layer is formed on a substrate. First and second gate trenches are formed in the dielectric layer. First and second spacers are disposed in the first and the second gate trenches, respectively. A patterned photoresist is formed on the dielectric layer. The patterned photoresist masks the first region and exposes the second region. Multiple cycles of spacer trimming process are performed to trim a sidewall profile of the second spacer. Each cycle comprises a step of oxygen stripping and a successive step of chemical oxide removal. The patterned photoresist is then removed to reveal the first region.Type: GrantFiled: June 28, 2019Date of Patent: June 15, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yao-Hsien Chung, Hao-Hsuan Chang, Ting-An Chien, Bin-Siang Tsai
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Patent number: 10892348Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.Type: GrantFiled: April 29, 2019Date of Patent: January 12, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hao-Hsuan Chang, Bin-Siang Tsai, Ting-An Chien, Yi-Liang Ye
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Publication number: 20200411681Abstract: A method for forming a semiconductor device is disclosed. A substrate having at least two fins thereon and an isolation trench between the at least two fins is provided. A liner layer is then deposited on the substrate. The liner layer conformally covers the two fins and interior surface of the isolation trench. A stress-buffer film is then deposited on the liner layer. The stress-buffer film completely fills a lower portion that is located at least below half of a trench depth of the isolation trench. A trench-fill oxide layer is then deposited to completely fill an upper portion of the isolation trench.Type: ApplicationFiled: June 25, 2019Publication date: December 31, 2020Inventors: Shih-Wei Su, Hao-Hsuan Chang, Chih-Wei Chang, Chi-Hsuan Cheng, Ting-An Chien, Bin-Siang Tsai